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公开(公告)号：US09917586B2
公开(公告)日：2018-03-13
申请号：US15611822
申请日：2017-06-02
申请人： MediaTek Inc.
发明人： Yang-Chuan Chen , Chi-Hsueh Wang , Hsiang-Hui Chang , Bo-Yu Lin
IPC分类号： H04L7/00 , H03K19/0175 , H03F3/217 , H04L27/34 , H04B1/04 , H04W24/02 , H04L25/02 , H04L25/08 , H03M1/12 , G01R21/06 , G01R23/00 , H03F1/24 , H04L27/20 , H03F1/02 , H03F3/24
CPC分类号： H03K19/017509 , G01R21/06 , G01R23/00 , H03F1/02 , H03F1/24 , H03F3/2178 , H03F3/24 , H03F2203/21154 , H03K19/017581 , H03M1/12 , H04B1/04 , H04B1/0475 , H04B2001/0408 , H04B2001/045 , H04L7/0037 , H04L7/0091 , H04L25/028 , H04L25/08 , H04L27/2053 , H04L27/2067 , H04L27/3411 , H04L27/3444 , H04W24/02
摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.
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公开(公告)号：US09698785B2
公开(公告)日：2017-07-04
申请号：US15255159
申请日：2016-09-02
申请人： MEDIATEK INC.
发明人： Yang-Chuan Chen , Chi-Hsueh Wang , Hsiang-Hui Chang , Bo-Yu Lin
IPC分类号： H04L7/00 , H03K19/0175 , H03F3/217 , H04L27/34 , H04B1/04 , H04W24/02 , H04L25/02 , H04L25/08 , H03M1/12 , G01R21/06 , G01R23/00 , H03F1/24 , H04L27/20
CPC分类号： H03K19/017509 , G01R21/06 , G01R23/00 , H03F1/02 , H03F1/24 , H03F3/2178 , H03F3/24 , H03F2203/21154 , H03K19/017581 , H03M1/12 , H04B1/04 , H04B1/0475 , H04B2001/0408 , H04B2001/045 , H04L7/0037 , H04L7/0091 , H04L25/028 , H04L25/08 , H04L27/2053 , H04L27/2067 , H04L27/3411 , H04L27/3444 , H04W24/02
摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.
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公开(公告)号：US09344143B2
公开(公告)日：2016-05-17
申请号：US13798042
申请日：2013-03-12
申请人： MEDIATEK INC.
发明人： Yen-Lin Huang , Hsiang-Hui Chang
CPC分类号： H04B1/64 , H03F1/3241 , H03F1/3247 , H03F3/189 , H03F3/24 , H03F2200/336 , H04B2001/0425
摘要： A signal transmitting device includes: a signal processing circuit arranged to process an input signal to generate a processed input signal according to a compensating signal; a signal converting circuit arranged to convert the processed input signal to generate an output signal according to an oscillating signal; and an arithmetic circuit arranged to generate the compensating signal according to the power of a predetermined component in the output signal, wherein the signal processing circuit uses the compensating signal to update the input signal, and the signal converting circuit converts the updated input signal to reduce the power of the predetermined component in the output signal.
摘要翻译： 信号发送装置包括：信号处理电路，被配置为根据补偿信号处理输入信号以产生经处理的输入信号; 信号转换电路，被配置为根据振荡信号转换经处理的输入信号以产生输出信号; 以及算术电路，被配置为根据输出信号中的预定分量的功率产生补偿信号，其中信号处理电路使用补偿信号来更新输入信号，并且信号转换电路转换更新的输入信号以减少 输出信号中预定分量的功率。
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公开(公告)号：US20160126892A1
公开(公告)日：2016-05-05
申请号：US14919847
申请日：2015-10-22
申请人： MEDIATEK Inc.
发明人： Yen Lin Huang , Hsiang-Hui Chang , Hsin-Hung Chen
CPC分类号： H03C3/20 , H02M3/07 , H03B5/1212 , H03B5/124 , H03B5/1265 , H03C3/0925 , H03C3/0941 , H03C3/0958 , H03L7/08 , H03L7/0802 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/104 , H03L7/1976 , H03L2207/06
摘要： A modulation circuit includes a phase locked loop (PLL) circuit, a scalar circuit and a sigma-delta modulator. The PLL circuit is for generating an output oscillating signal in response to a reference signal, a first control signal and a second control signal. The scalar circuit is for generating the first control signal in response to modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form. The sigma-delta modulator is for generating the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit.
摘要翻译： 调制电路包括锁相环（PLL）电路，标量电路和Σ-Δ调制器。 PLL电路用于响应于参考信号，第一控制信号和第二控制信号产生输出振荡信号。 标量电路用于响应于调制数据产生第一控制信号以控制输出振荡信号的频率偏差，其中第一控制信号是数字形式。 Σ-Δ调制器用于根据调制数据产生第二控制信号，以调制PLL电路的分频器的分频值。
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公开(公告)号：US20140348264A1
公开(公告)日：2014-11-27
申请号：US14281902
申请日：2014-05-20
申请人： MEDIATEK INC.
发明人： Wen-Chieh Wang , Chi-Hsueh Wang , Hsiang-Hui Chang , I-Wen Liu , Khurram Muhammad , Chih-Ming Hung
CPC分类号： H03K19/017509 , G01R21/06 , G01R23/00 , H03F1/02 , H03F1/24 , H03F3/2178 , H03F3/24 , H03F2203/21154 , H03K19/017581 , H03M1/12 , H04B1/04 , H04B1/0475 , H04B2001/0408 , H04B2001/045 , H04L7/0037 , H04L7/0091 , H04L25/028 , H04L25/08 , H04L27/2053 , H04L27/2067 , H04L27/3411 , H04L27/3444 , H04W24/02
摘要： A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.
摘要翻译： 数字发射机包括：多个可调延迟线，其布置成通过多个延迟时间来延迟多个数字输入信号，以分别产生多个延迟的数字输入信号; 多个转换装置，被配置为分别将多个延迟的数字输入信号转换成多个转换信号; 以及校准装置，其布置成调整多个可调延迟线中的至少一个可调节延迟线的延迟时间，以使多个转换装置在相应的期望时间点转换多个延迟的数字输入信号。
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6.发明申请SWITCHING POWER AMPLIFIER AND METHOD FOR CONTROLLING THE SWITCHING POWER AMPLIFIER 有权切换功率放大器和控制开关功率放大器的方法公开(公告)号：US20140347127A1
公开(公告)日：2014-11-27
申请号：US14267929
申请日：2014-05-02
申请人： Mediatek Inc.
发明人： Yang-Chuan Chen , Hsiang-Hui Chang
IPC分类号： H03F3/217
CPC分类号： H03K19/017509 , G01R21/06 , G01R23/00 , H03F1/02 , H03F1/24 , H03F3/2178 , H03F3/24 , H03F2203/21154 , H03K19/017581 , H03M1/12 , H04B1/04 , H04B1/0475 , H04B2001/0408 , H04B2001/045 , H04L7/0037 , H04L7/0091 , H04L25/028 , H04L25/08 , H04L27/2053 , H04L27/2067 , H04L27/3411 , H04L27/3444 , H04W24/02
摘要： A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.
摘要翻译： 开关功率放大器包括：由第一数字信号控制的第一晶体管，以选择性地输出第一输出信号; 由第二数字信号控制的第二晶体管，以选择性地输出第二输出信号; 以及控制电路，被配置为根据第一数字信号和第三数字信号产生第二数字信号; 其中所述第一输出信号和所述第二输出信号在所述第一晶体管和所述第二晶体管的公共连接的节点上输出。
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公开(公告)号：US20130188675A1
公开(公告)日：2013-07-25
申请号：US13744385
申请日：2013-01-17
申请人： MEDIATEK INC.
IPC分类号： H04B17/00
摘要： A communication device with a power detection scheme is disclosed. The communication device includes a transmitter for transmitting an RF signal, a demodulator for demodulating the RF signal by utilizing a phase-modulated (PM) signal provided from the transmitter to generate a demodulated signal, a loopback circuit coupled between the transmitter and the demodulator for transmitting the RF signal and the PM signal from the transmitter to the demodulator when the power detection scheme is enabled, and a power detector for detecting power of the demodulated signal.
摘要翻译： 公开了具有功率检测方案的通信设备。 通信设备包括用于发送RF信号的发射机，用于通过利用从发射机提供的相位调制（PM）信号来解调RF信号以产生解调信号的解调器，耦合在发射机和解调器之间的环回电路， 当功率检测方案被使能时，将RF信号和PM信号从发射机发送到解调器;以及功率检测器，用于检测解调信号的功率。
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8.发明公开公开(公告)号：US20240179555A1
公开(公告)日：2024-05-30
申请号：US18515302
申请日：2023-11-21
申请人： MEDIATEK INC.
发明人： Huan-Ren Fu , Aijun Cao , Hsiang-Hui Chang
IPC分类号： H04W24/10
CPC分类号： H04W24/10
摘要： A method for signaling an improved receive (Rx) performance report of victim bands includes: configuring a signaling message to indicate the improved Rx performance report, and sending the signaling message. The improved Rx performance report includes information of K improved Rx performance indicators being only a subset of M improved Rx performance indicators of a user equipment (UE), where K and M are positive integers, M is larger than K, and K is not smaller than one.
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公开(公告)号：US09876501B2
公开(公告)日：2018-01-23
申请号：US14267929
申请日：2014-05-02
申请人： MEDIATEK INC.
发明人： Yang-Chuan Chen , Hsiang-Hui Chang
IPC分类号： H03F3/217 , H03K19/0175 , H04L27/34 , H04B1/04 , H04W24/02 , H04L25/02 , H04L25/08 , H03M1/12 , H04L7/00 , G01R21/06 , G01R23/00 , H03F1/24 , H04L27/20
CPC分类号： H03K19/017509 , G01R21/06 , G01R23/00 , H03F1/02 , H03F1/24 , H03F3/2178 , H03F3/24 , H03F2203/21154 , H03K19/017581 , H03M1/12 , H04B1/04 , H04B1/0475 , H04B2001/0408 , H04B2001/045 , H04L7/0037 , H04L7/0091 , H04L25/028 , H04L25/08 , H04L27/2053 , H04L27/2067 , H04L27/3411 , H04L27/3444 , H04W24/02
摘要： A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.
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公开(公告)号：US09172408B2
公开(公告)日：2015-10-27
申请号：US14037329
申请日：2013-09-25
申请人： MEDIATEK INC.
发明人： Hsiang-Hui Chang , Li-Shin Lai , Chih-Jung Chen , Chih-Hao Sun
CPC分类号： H04B1/0475 , H04B1/0483 , H04L27/04
摘要： A transmitter includes a first channel and a second channel. The first channel includes a first mixer, and is used for processing a first input signal to generate a first output signal; the second channel includes a second mixer, where the second channel does not receive any input signal. When the transmitter is operated under a first mode, both the first mixer and the second mixer receive oscillation signals.
摘要翻译： 发射机包括第一信道和第二信道。 第一通道包括第一混频器，用于处理第一输入信号以产生第一输出信号; 第二通道包括第二混频器，其中第二通道不接收任何输入信号。 当发射机在第一模式下操作时，第一混频器和第二混频器都接收振荡信号。
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