公开(公告)号：US12087355B2

公开(公告)日：2024-09-10

申请号：US17936559

申请日：2022-09-29

Applicant: MEDIATEK INC.

Inventor： Dao-Ping Wang

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: An adaptive control circuit of SRAM (Static Random Access Memory) includes a switch circuit, a forward diode-connected transistor, a backward diode-connected transistor, and a first delay circuit. The switch circuit is supplied by a supply voltage, and is coupled to a first node. The backward diode-connected transistor is coupled in parallel with the forward diode-connected transistor between the first node and a second node. The first delay circuit is coupled between the second node and a ground voltage.

公开(公告)号：US10176853B2

公开(公告)日：2019-01-08

申请号：US15499876

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Chi-Hao Hong ,  Dao-Ping Wang ,  Yi-Wei Chen ,  Yi-Ping Kuo ,  Shu-Lin Lai

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/10 ,  G11C7/08

Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.

公开(公告)号：US20170345469A1

公开(公告)日：2017-11-30

申请号：US15499876

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Chi-Hao Hong ,  Dao-Ping Wang ,  Yi-Wei Chen ,  Yi-Ping Kuo ,  Shu-Lin Lai

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/109

Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.

公开(公告)号：US09640229B2

公开(公告)日：2017-05-02

申请号：US14692057

申请日：2015-04-21

Applicant: MediaTek Inc.

Inventor： Dao-Ping Wang ,  Chia-Wei Wang

IPC: G11C5/06 ,  G11C7/06 ,  G11C7/00 ,  G11C16/12 ,  G11C17/12 ,  G11C17/14 ,  G11C11/56 ,  G11C5/14

CPC classification number: G11C7/06 ,  G11C5/06 ,  G11C5/063 ,  G11C5/14 ,  G11C7/00 ,  G11C11/5692 ,  G11C16/12 ,  G11C17/12 ,  G11C17/14

Abstract: A memory circuit includes a transistor, a signal line and a plurality of information lines. The transistor includes a first electrode, a second electrode and a control electrode. The transistor is included in a memory cell. The signal line is connected to the first electrode of the transistor. The voltage on the signal line is programmable. At most one of the information lines is connected to the second electrode of the transistor via a contact. Information stored in the memory cell is coded according to the voltage programmed on the signal line and an option of which information line the contact should connect to the second electrode of the transistor.