公开(公告)号：US20100323511A1

公开(公告)日：2010-12-23

申请号：US12872192

申请日：2010-08-31

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L21/336

CPC classification number: H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42344

Abstract: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.

Abstract translation: 非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。 凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

公开(公告)号：US20090159957A1

公开(公告)日：2009-06-25

申请号：US11961183

申请日：2007-12-20

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42344

Abstract: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.

Abstract translation: 非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。 凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

公开(公告)号：US07808032B2

公开(公告)日：2010-10-05

申请号：US12145681

申请日：2008-06-25

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7854 ,  H01L29/7881

Abstract: A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

Abstract translation: 浮动栅极存储单元的沟道区域（104）至少部分地位于半导体衬底的鳍状突起（110P）中。 浮栅的顶面可以沿着突起的至少两侧下降到突起的顶部（110P-T）的下方。 控制门的底面也可能下降至低于突起顶部的水平。 浮动门的底面可能下降到突起顶部以下至少50％的高度。 将浮动栅极与突起分离的电介质（120）可以在突起的顶部处至少与在突起的顶部下方的突起高度的至少50％的水平（L2）相同。 存储器和非存储器集成电路中的非常狭窄的鳍或其他窄特征可以通过提供第一层（320）然后从第二层形成间隔物（330）而形成，而不需要在由第一层制成的特征的侧壁上进行光刻。 然后在相邻间隔物之间​​的区域中形成窄鳍片或其它特征，而无需进一步的光刻。 更具体地，在这些区域中形成第三层（340），并且第一层和间隔物被选择性地去除到第三层。 第三层用作掩模以形成窄特征。

公开(公告)号：US20090101961A1

公开(公告)日：2009-04-23

申请号：US11876557

申请日：2007-10-22

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/7881 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure provides a memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, a tantalum-nitride layer, and a control gate layer. When a positive bias is applied to the control gate and the select gate, negative charges are injected from a channel region of a substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the negative charges in the charge storage layer. When a negative bias is applied to the control gate, negative charges are tunneled from the charge storage layer to the channel region of the substrate through the tunneling dielectric layer.

Abstract translation: 本公开提供了一种存储器件，其具有与单元堆叠相邻形成的单元堆叠和选择栅极。 电池堆包括隧道介电层，电荷存储层，阻挡介电层，氮化钽层和控制栅层。 当向控制栅极和选择栅极施加正偏压时，从衬底的沟道区域通过隧道电介质层注入负电荷并进入电荷存储层，从而将负电荷存储在电荷存储层中。 当向控制栅极施加负偏压时，负电荷通过隧道电介质层从电荷存储层隧穿到衬底的沟道区。

公开(公告)号：US06495411B1

公开(公告)日：2002-12-17

申请号：US09686842

申请日：2000-10-10

Applicant: Len Mei

Inventor： Len Mei

IPC: H01L218242

CPC classification number: H01L27/1087 ,  H01L21/30608 ,  H01L21/3086 ,  H01L28/84 ,  Y10S438/964

Abstract: A method for fabricating deep-submicron DRAMs containing a deep trench capacitor with enlarged sidewall surface for improved storage capacitance. It includes the main steps of: (a) forming a silicon substrate having a (110) crystalline plane and a (111) crystalline plane; (b) forming a vertically extending deep trench into a crystalline silicon substrate; (c) filling the deep trench with a first dielectric material to form a first dielectric filler layer; (d) etching back the first dielectric filler layer to a first depth; (e) forming a dielectric collar from a second dielectric material which hangs on the sidewall of the deep trench extending from the opening of the trench to the first depth; (f) removing the first dielectric filler layer with a selective etching process; and (g) under a carefully timed exposure, using an isotropic etching solution which has high etching rate in the (110) plane and low etching rate in the (111) plane to form a roughened surface on the bottom surface of the deep trench. A roughened surface has a root-mean-square (RMS) surface roughness of at least 100 Å can be obtained. Since this method does not require enlargement in either the vertical direction or the horizontal direction (as in the case of bottle-shaped deep trenches), it is most advantageous for use in advanced DRAM manufacturing processes, especially those process with feature sizes of 0.15 &mgr;m and below.

Abstract translation: 一种用于制造深亚微米DRAM的方法，其包含具有扩大侧壁表面的深沟槽电容器，以改善存储电容。 它包括以下主要步骤：（a）形成具有（110）晶面和（111）晶面的硅衬底; （b）在晶体硅衬底中形成垂直延伸的深沟槽; （c）用第一介电材料填充深沟槽以形成第一介电填料层; （d）将第一介电填料层回蚀刻到第一深度; （e）从第二电介质材料形成介质套管，所述第二电介质材料悬挂在从所述沟槽的开口延伸到所述第一深度的所述深沟槽的侧壁上; （f）用选择性蚀刻工艺除去第一介电填料层; （g）在精心定时的曝光下，使用在（110）面具有高蚀刻速率的各向同性蚀刻溶液，并且（111）面中的蚀刻速率低，在深沟槽的底表面上形成粗糙表面。 可以获得粗糙表面的均方根（RMS）表面粗糙度至少为100埃。 由于该方法不需要在垂直方向或水平方向上放大（如在瓶形深沟槽的情况下），所以最有利的是用于先进的DRAM制造工艺，特别是特征尺寸为0.15μm的那些工艺 及以下。

公开(公告)号：US07816726B2

公开(公告)日：2010-10-19

申请号：US11961183

申请日：2007-12-20

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42344

Abstract: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.

Abstract translation: 非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。 凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

公开(公告)号：US20090184359A1

公开(公告)日：2009-07-23

申请号：US12017961

申请日：2008-01-22

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/42344

Abstract: A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second nitride layer, a control gate formed on the high-K oxide layer, and a poly spacer as the select gate formed adjacent to the control gate.

Abstract translation: 具有与单元堆叠相邻形成的单元堆叠和选择栅极的存储器件。 电池堆包括形成在衬底的沟道区上的第一无陷波氮化物层，形成在第一氮化物层上的第二氮化物层，形成在第二氮化物层上的氧化物层， K氧化物层和作为选择栅极的多隔板作为与控制栅极相邻形成。

公开(公告)号：US20050205411A1

公开(公告)日：2005-09-22

申请号：US10710698

申请日：2004-07-29

Applicant: Tai-Yuan Chen ,  Len Mei

Inventor： Tai-Yuan Chen ,  Len Mei

IPC: C23C14/04 ,  C23C14/35 ,  H01J37/34

CPC classification number: H01J37/3405 ,  C23C14/046 ,  C23C14/351

Abstract: A physical vapor deposition apparatus is provided. The physical vapor deposition apparatus comprises: a reaction chamber; and an electromagnet magnetron device disposed above and outside said reaction chamber, wherein when performing a physical vapor deposition process, the magnetic poles of said electromagnet magnetron device are reversed in-situ to reduce the possibility of asymmetric deposition of the thin film on the sidewalls of the opening.

Abstract translation: 提供了一种物理气相沉积装置。 物理气相沉积装置包括：反应室; 以及设置在所述反应室上方和外部的电磁磁控管装置，其中当进行物理气相沉积工艺时，所述电磁磁控管装置的磁极在原地反向以减少薄膜不对称沉积在侧壁上的可能性 开幕。

公开(公告)号：US06232171B1

公开(公告)日：2001-05-15

申请号：US09327872

申请日：1999-06-08

Applicant: Len Mei

Inventor： Len Mei

IPC: H01L218242

CPC classification number: H01L27/1087 ,  H01L29/66181

Abstract: A method for fabricating deep-submicron vertically arranged capacitors is disclosed which allows the capacitor to enjoy an enhanced sidewall surface so as to attain a capacitance of 40 pF or more. The method comprises the steps of: (a) forming an elongated trench into an active region of a substrate, the elongated trench having a sidewall defining the trench inside the substrate; (b) forming a oxide filler layer which fills the deep trench; (c) etching the oxide filler layer to a predetermined depth, to reveal an upper portion of the sidewall above the predetermined depth; (d) forming a nitride sidewall spacer cover the upper portion of the sidewall; (e) etching away the oxide filler layer to reveal the lower portion of the sidewall; (f) using the sidewall spacer as a mask to either selectively etch away the lower portion of the sidewall or cause the lower portion of the sidewall to be subject to a chemical reaction so that the lower portion of the sidewall can be etched away and thus causing the trench width in the lower portion to be enlarged; and (g) removing the chemically altered lower portion of the sidewall if it is not already removed, to form a bottle-shaped deep trench having an enhanced sidewall surface at the lower portion. The sidewall space may be removed or it may remain in the deep trench to prevent leakage.

Abstract translation: 公开了一种用于制造深亚微米垂直布置的电容器的方法，其允许电容器享受增强的侧壁表面，以便获得40pF或更大的电容。 该方法包括以下步骤：（a）将细长的沟槽形成到衬底的有源区域中，所述细长沟槽具有限定衬底内的沟槽的侧壁; （b）形成填充深沟槽的氧化物填充层; （c）将氧化物填充层蚀刻到预定深度，以暴露出超过预定深度的侧壁的上部; （d）形成氮化物侧壁间隔物覆盖侧壁的上部; （e）蚀刻掉氧化物填充层以露出侧壁的下部; （f）使用侧壁间隔件作为掩模来选择性地蚀刻掉侧壁的下部，或者导致侧壁的下部遭受化学反应，使得侧壁的下部可被蚀刻掉，因此 导致下部的沟槽宽度增大; 和（g）如果尚未移除侧壁的化学改变的下部，则移除，以形成在下部具有增强的侧壁表面的瓶形深沟槽。 侧壁空间可以被去除，或者它可以保留在深沟槽中以防止泄漏。

公开(公告)号：US08125020B2

公开(公告)日：2012-02-28

申请号：US11872477

申请日：2007-10-15

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L29/792 ,  H01L29/788

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66833

Abstract: A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias to the control gate directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.

Abstract translation: 存储器件包括与电池堆相邻形成的电池堆和选择栅。 电池堆包括隧道介电层，电荷存储层，阻挡介质层和控制栅极。 对控制栅极施加正偏压，器件的选择栅极和源极通过在选择栅极和控制器之间的间隙附近的位置处的隧道电介质层通过热电子注入从衬底的沟道区域注入负电荷 门进入电荷存储层以在电荷存储层中存储负电荷。 将负偏压施加到控制栅极直接从衬底的沟道区通过隧道电介质层引导正电荷并进入电荷存储层，以在电荷存储层中存储正电荷。