A method for fabricating deep-submicron DRAMs containing a deep trench capacitor with enlarged sidewall surface for improved storage capacitance. It includes the main steps of: (a) forming a silicon substrate having a (110) crystalline plane and a (111) crystalline plane; (b) forming a vertically extending deep trench into a crystalline silicon substrate; (c) filling the deep trench with a first dielectric material to form a first dielectric filler layer; (d) etching back the first dielectric filler layer to a first depth; (e) forming a dielectric collar from a second dielectric material which hangs on the sidewall of the deep trench extending from the opening of the trench to the first depth; (f) removing the first dielectric filler layer with a selective etching process; and (g) under a carefully timed exposure, using an isotropic etching solution which has high etching rate in the (110) plane and low etching rate in the (111) plane to form a roughened surface on the bottom surface of the deep trench. A roughened surface has a root-mean-square (RMS) surface roughness of at least 100 Å can be obtained. Since this method does not require enlargement in either the vertical direction or the horizontal direction (as in the case of bottle-shaped deep trenches), it is most advantageous for use in advanced DRAM manufacturing processes, especially those process with feature sizes of 0.15 &mgr;m and below.