公开(公告)号：US07816726B2

公开(公告)日：2010-10-19

申请号：US11961183

申请日：2007-12-20

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42344

Abstract: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.

Abstract translation: 非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。 凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

公开(公告)号：US20090184359A1

公开(公告)日：2009-07-23

申请号：US12017961

申请日：2008-01-22

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/42344

Abstract: A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second nitride layer, a control gate formed on the high-K oxide layer, and a poly spacer as the select gate formed adjacent to the control gate.

Abstract translation: 具有与单元堆叠相邻形成的单元堆叠和选择栅极的存储器件。 电池堆包括形成在衬底的沟道区上的第一无陷波氮化物层，形成在第一氮化物层上的第二氮化物层，形成在第二氮化物层上的氧化物层， K氧化物层和作为选择栅极的多隔板作为与控制栅极相邻形成。

公开(公告)号：US08125020B2

公开(公告)日：2012-02-28

申请号：US11872477

申请日：2007-10-15

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L29/792 ,  H01L29/788

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66833

Abstract: A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias to the control gate directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.

Abstract translation: 存储器件包括与电池堆相邻形成的电池堆和选择栅。 电池堆包括隧道介电层，电荷存储层，阻挡介质层和控制栅极。 对控制栅极施加正偏压，器件的选择栅极和源极通过在选择栅极和控制器之间的间隙附近的位置处的隧道电介质层通过热电子注入从衬底的沟道区域注入负电荷 门进入电荷存储层以在电荷存储层中存储负电荷。 将负偏压施加到控制栅极直接从衬底的沟道区通过隧道电介质层引导正电荷并进入电荷存储层，以在电荷存储层中存储正电荷。

公开(公告)号：US20090321806A1

公开(公告)日：2009-12-31

申请号：US12146933

申请日：2008-06-26

Applicant: Len Mei ,  Yue-Song He

Inventor： Len Mei ,  Yue-Song He

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/28114

Abstract: Substrate isolation regions (570) initially protrude upward above a semiconductor substrate (520) but are later etched down. Before they are etched down, floating gate layer (590) is deposited and etched or polished off the top surfaces of the substrate isolation regions. The floating gate layer thus has upward protrusions overlying sidewalls of the substrate isolation regions. When the substrate isolation regions are etched down, the floating gate layer's upward protrusions' outer sidewalls become exposed. The upward protrusions serve to increase the capacitance between the floating and control gates. The floating gates' bottom surfaces are restricted to the active areas (564) not to overlie the substrate isolation regions. Other features are also provided.

Abstract translation: 衬底隔离区（570）最初在半导体衬底（520）上方向上突出，但是后来被刻蚀掉。 在蚀刻之前，浮栅层（590）被沉积并蚀刻或抛光离开衬底隔离区域的顶表面。 因此，浮栅层具有覆盖衬底隔离区的侧壁的向上突起。 当衬底隔离区被蚀刻时，浮栅层的向上突起的外侧壁变得暴露。 向上的凸起用于增加浮动和控制门之间的电容。 浮动栅极的底表面限于不覆盖衬底隔离区的有源区（564）。 还提供其他功能。

公开(公告)号：US20090096013A1

公开(公告)日：2009-04-16

申请号：US11872477

申请日：2007-10-15

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66833

Abstract: A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias is to the control gates directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.

Abstract translation: 存储器件包括与电池堆相邻形成的电池堆和选择栅。 电池堆包括隧道介电层，电荷存储层，阻挡介质层和控制栅极。 对控制栅极施加正偏压，器件的选择栅极和源极通过在选择栅极和控制器之间的间隙附近的位置处的隧道电介质层通过热电子注入从衬底的沟道区域注入负电荷 门进入电荷存储层以在电荷存储层中存储负电荷。 施加负偏压是控制栅极直接从衬底的通道区域通过隧穿介电层隧穿正电荷并进入电荷存储层，以在电荷存储层中存储正电荷。

公开(公告)号：US20090256221A1

公开(公告)日：2009-10-15

申请号：US12101908

申请日：2008-04-11

Applicant: Len Mei ,  Yue-Song He

Inventor： Len Mei ,  Yue-Song He

IPC: H01L29/82 ,  H01L21/306

CPC classification number: H01L21/32139 ,  B82Y10/00 ,  B82Y25/00 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/222

Abstract: A method for forming very small isolated dots of a target material, e.g., a ferromagnetic material or phase change material, on a substrate includes providing a substrate having a layer of the target material disposed on a surface thereof, etching the layer of target material so as to form a plurality of lines of the material on the surface of the substrate, and etching the lines of the target material so as to form a rectangular matrix of substantially similar, very small isolated dots of the target material on the substrate. By the successive formation of orthogonally intersecting linear patterns on the substrate, including the formation and use of “hard” etch masks, spacer approach and selective etching techniques, the method enables very small (

Abstract translation: 在衬底上形成目标材料（例如铁磁材料或相变材料）的非常小的孤立点的方法包括提供具有设置在其表面上的目标材料层的衬底，蚀刻靶材料层 以在衬底的表面上形成多条材料线，并蚀刻目标材料的线以便形成基板上目标材料基本相似的非常小的孤立点的矩形矩阵。 通过在衬底上连续形成正交相交的线性图案，包括形成和使用“硬”蚀刻掩模，间隔法和选择性蚀刻技术，该方法使目标材料的非常小的（<65nm）孤立点为 通过使用常规的193nm波长光刻方法和装置可靠地形成在基板上。

公开(公告)号：US20090251972A1

公开(公告)日：2009-10-08

申请号：US12062037

申请日：2008-04-03

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: G11C16/04 ,  H01L21/336 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L29/42344 ,  H01L29/792

Abstract: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.

Abstract translation: 非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。 凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

公开(公告)号：US07452776B1

公开(公告)日：2008-11-18

申请号：US11739482

申请日：2007-04-24

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L21/8247

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7854 ,  H01L29/7881

Abstract: A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

Abstract translation: 浮栅存储单元的沟道区（104）至少部分地位于半导体衬底的鳍状突起（110P）中。 浮栅的顶面可以沿着突起的至少两侧下降到突起的顶部（110P-T）下方的水平面。 控制门的底面也可能下降至低于突起顶部的水平。 浮动门的底面可能下降到突起顶部以下至少50％的高度。 将浮动栅极与突起分离的电介质（120）可以在突起的顶部处至少与在突起的顶部下方高达突起高度的50％的水平面（L 2）一样厚。 存储器和非存储器集成电路中的非常狭窄的鳍或其他窄特征可以通过提供第一层（320）然后从第二层形成间隔物（330）而形成，而不需要在由第一层制成的特征的侧壁上进行光刻。 然后在相邻间隔物之间​​的区域中形成窄鳍片或其它特征，而无需进一步的光刻。 更具体地，在这些区域中形成第三层（340），并且第一层和间隔物被选择性地去除到第三层。 第三层用作掩模以形成窄特征。

公开(公告)号：US20080266949A1

公开(公告)日：2008-10-30

申请号：US11739482

申请日：2007-04-24

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: G11C11/34 ,  H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7854 ,  H01L29/7881

Abstract: A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

Abstract translation: 浮栅存储单元的沟道区（104）至少部分地位于半导体衬底的鳍状突起（110P）中。 浮栅的顶面可以沿着突起的至少两侧下降到突起的顶部（110P-T）下方的水平面。 控制门的底面也可能下降至低于突起顶部的水平。 浮动门的底面可能下降到突起顶部以下至少50％的高度。 将浮动栅极与突起分离的电介质（120）可以在突起的顶部处至少与在突起的顶部下方高达突起高度的50％的水平面（L 2）一样厚。 存储器和非存储器集成电路中的非常狭窄的鳍或其他窄特征可以通过提供第一层（320）然后从第二层形成间隔物（330）而形成，而不需要在由第一层制成的特征的侧壁上进行光刻。 然后在相邻间隔物之间​​的区域中形成窄鳍片或其它特征，而无需进一步的光刻。 更具体地，在这些区域中形成第三层（340），并且第一层和间隔物被选择性地去除到第三层。 第三层用作掩模以形成窄特征。

公开(公告)号：US20080265305A1

公开(公告)日：2008-10-30

申请号：US12145681

申请日：2008-06-25

Applicant: Yue-Song He ,  Len Mei

Inventor： Yue-Song He ,  Len Mei

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7854 ,  H01L29/7881

Abstract: A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.