公开(公告)号：US20180342399A1

公开(公告)日：2018-11-29

申请号：US16053978

申请日：2018-08-03

Applicant: Lam Research Corporation

Inventor： Daniel Peter ,  Samantha Tan ,  Reza Arghavani ,  Yang Pan

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/30604 ,  H01L21/02057 ,  H01L21/306 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/31058 ,  H01L21/31111

Abstract: A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.

公开(公告)号：US20180269061A1

公开(公告)日：2018-09-20

申请号：US15976793

申请日：2018-05-10

Applicant: Lam Research Corporation

Inventor： Reza Arghavani ,  Samantha Tan ,  Bhadri N. Varadarajan ,  Adrien LaVoie ,  Ananda K. Banerji ,  Jun Qian ,  Shankar Swaminathan

IPC: H01L21/223 ,  C23C16/52 ,  H01L21/67 ,  C23C16/455 ,  H01L21/22 ,  H01L21/225 ,  C23C16/04 ,  H01L29/66 ,  C23C16/50

CPC classification number: H01L21/223 ,  C23C16/045 ,  C23C16/45529 ,  C23C16/45544 ,  C23C16/50 ,  C23C16/52 ,  H01L21/2225 ,  H01L21/2252 ,  H01L21/67155 ,  H01L21/67207 ,  H01L29/66803

Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

公开(公告)号：US20160181117A1

公开(公告)日：2016-06-23

申请号：US14612095

申请日：2015-02-02

Applicant: Lam Research Corporation

Inventor： Reza Arghavani ,  Shashank C. Deshmukh ,  Eric A. Hudson ,  Tom Kamp ,  Samantha Tan ,  Gerardo Adrian Delgadino

IPC: H01L21/311 ,  H01L21/67 ,  H01J37/32 ,  H01L21/263

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/32899 ,  H01L21/6719 ,  H01L21/67213 ,  H01L21/76897

Abstract: The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.

Abstract translation: 本文的实施例涉及用于蚀刻电介质材料中凹陷特征的方法和装置。 在各种实施例中，在两个蚀刻操作中形成凹陷特征。 第一蚀刻操作部分地蚀刻特征并且可以在配置成产生电容耦合等离子体的反应器中进行。 第一蚀刻操作可能在底层半导体材料由于穿过半导体材料顶部的电介质的离子穿透而经受显着的损坏之前结束。 第二蚀刻操作可以在配置成产生电感耦合等离子体的反应器中进行。 第一和第二蚀刻操作本身可以是多步循环过程。

公开(公告)号：US20190385850A1

公开(公告)日：2019-12-19

申请号：US16556122

申请日：2019-08-29

Applicant: Lam Research Corporation

Inventor： Reza Arghavani ,  Samantha Tan ,  Bhadri N. Varadarajan ,  Adrien LaVoie ,  Ananda K. Banerji ,  Jun Qian ,  Shankar Swaminathan

IPC: H01L21/223 ,  H01L21/22 ,  C23C16/52 ,  C23C16/455 ,  H01L21/67 ,  H01L29/66 ,  H01L21/225 ,  C23C16/04 ,  C23C16/50

Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

公开(公告)号：US09997357B2

公开(公告)日：2018-06-12

申请号：US14194549

申请日：2014-02-28

Applicant: Lam Research Corporation

Inventor： Reza Arghavani ,  Samantha Tan ,  Bhadri N. Varadarajan ,  Adrien LaVoie ,  Ananda Banerji ,  Jun Qian ,  Shankar Swaminathan

IPC: H01L21/223 ,  H01L21/22 ,  C23C16/52 ,  C23C16/455 ,  H01L21/67 ,  H01L21/225 ,  C23C16/04 ,  H01L29/66 ,  C23C16/50

CPC classification number: H01L21/223 ,  C23C16/045 ,  C23C16/45529 ,  C23C16/45544 ,  C23C16/50 ,  C23C16/52 ,  H01L21/2225 ,  H01L21/2252 ,  H01L21/67155 ,  H01L21/67207 ,  H01L29/66803

Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

公开(公告)号：US20170287724A1

公开(公告)日：2017-10-05

申请号：US15377359

申请日：2016-12-13

Applicant: Lam Research Corporation

Inventor： Daniel Peter ,  Samantha Tan ,  Reza Arghavani ,  Yang Pan

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L21/30604 ,  H01L21/02057 ,  H01L21/306 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/31058 ,  H01L21/31111

Abstract: A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.

公开(公告)号：US20160379826A9

公开(公告)日：2016-12-29

申请号：US14194549

申请日：2014-02-28

Applicant: LAM RESEARCH CORPORATION

Inventor： Reza Arghavani ,  Samantha Tan ,  Bhadri N. Varadarajan ,  Adrien LaVoie ,  Ananda Banerji ,  Jun Qian ,  Shankar Swaminathan

IPC: H01L21/223 ,  C23C16/455 ,  C23C16/52 ,  C23C16/50 ,  H01L21/22 ,  H01L21/67

CPC classification number: H01L21/223 ,  C23C16/045 ,  C23C16/45529 ,  C23C16/45544 ,  C23C16/50 ,  C23C16/52 ,  H01L21/2225 ,  H01L21/2252 ,  H01L21/67155 ,  H01L21/67207 ,  H01L29/66803

Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

公开(公告)号：US20160056037A1

公开(公告)日：2016-02-25

申请号：US14464475

申请日：2014-08-20

Applicant: Lam Research Corporation

Inventor： Shruti Vivek Thombare ,  Ishtak Karim ,  Sanjay Gopinath ,  Reza Arghavani ,  Michal Danek

IPC: H01L21/02 ,  C23C16/455 ,  H01J37/32 ,  C23C16/505 ,  C23C16/458 ,  C23C16/40 ,  H01L21/324 ,  C23C16/52

CPC classification number: H01L21/02186 ,  C23C16/06 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45544 ,  C23C16/458 ,  C23C16/505 ,  C23C16/52 ,  C23C16/56 ,  H01J37/32082 ,  H01J37/32449 ,  H01J37/32724 ,  H01L21/02238 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/0415 ,  H01L21/044 ,  H01L21/324 ,  H01L29/66068

Abstract: Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.

Abstract translation: 提供沉积和调整亚化学计量氧化钛沉积的方法。 方法包括通过（i）将基底暴露于四碘化钛，（ii）吹扫室，（iii）将基板暴露于等离子体，（iv）吹扫室，（ v）重复（i）至（iv），以及处理基底上沉积的钛以形成亚化学计量的氧化钛。 在将钛沉积在基底上之前，也可以沉积氧化钛。 处理包括底物暴露于氧源和/或退火底物。

公开(公告)号：US10559468B2

公开(公告)日：2020-02-11

申请号：US15976793

申请日：2018-05-10

Applicant: Lam Research Corporation

Inventor： Reza Arghavani ,  Samantha Tan ,  Bhadri N. Varadarajan ,  Adrien LaVoie ,  Ananda K. Banerji ,  Jun Qian ,  Shankar Swaminathan

IPC: H01L21/223 ,  H01L21/22 ,  H01L21/225 ,  C23C16/52 ,  C23C16/455 ,  H01L21/67 ,  H01L29/66 ,  C23C16/04 ,  C23C16/50

Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon carbonitride material, silicon oxycarbide material, silicon carbon-oxynitride, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

公开(公告)号：US10068981B2

公开(公告)日：2018-09-04

申请号：US15059208

申请日：2016-03-02

Applicant: Lam Research Corporation

Inventor： Yunsang Kim ,  Reza Arghavani

IPC: H01L21/324 ,  H01L29/66 ,  H01L21/225 ,  H01L29/45 ,  H01L21/285 ,  H01L21/288

Abstract: Methods of doping semiconductor substrates using deposition of a rare earth metal-containing film such as an yttrium-containing film, and annealing techniques are provided herein. Rare earth metal-containing films are deposited using gas, liquid, or solid precursors without a bias and may be deposited conformally. Some embodiments may involve deposition using a plasma. Substrates may be annealed at temperatures less than about 500° C.