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    Microfeature dies with porous regions, and associated methods and systems
    2.
    发明申请
    Microfeature dies with porous regions, and associated methods and systems 审中-公开
    具有多孔区域的微特征，以及相关的方法和系统

    公开(公告)号：US20070099397A1

    公开(公告)日：2007-05-03

    申请号：US11634417

    申请日：2006-12-04

    Applicant: Kyle Kirby ,  Paul Morgan

    Inventor： Kyle Kirby ,  Paul Morgan

    IPC: H01L21/00

    CPC classification number: H01L21/76898 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02351 ,  H01L21/31695 ,  H01L21/743 ,  H01L21/78

    Abstract: Microfeature dies with porous regions, and associated methods and systems are disclosed. A method in accordance with one embodiment of the invention includes forming a porous region between a die and a remainder portion of a microfeature workpiece, and separating the die from the remainder portion by removing at least a portion of the porous region. For example, the die can be removed from the remainder portion by making a cut at the porous region (e.g., with a rotating saw blade), etching material from the porous region, or directing a water jet at the porous region. In other embodiments, a porous region of the microfeature workpiece can receive conductive material to form a conductive pathway (e.g., a line and/or via) in the workpiece. In still further embodiments, the porous regions of the workpiece can be formed electrolytically with electrodes that are spaced apart from the workpiece and/or support relative movement between the electrodes and the workpiece.

    Abstract translation: 具有多孔区域的微特征模具以及相关方法和系统被公开。 根据本发明的一个实施例的方法包括在模具和微特征工件的剩余部分之间形成多孔区域，并且通过去除多孔区域的至少一部分将模具与其余部分分离。 例如，通过在多孔区域（例如，利用旋转的锯片）进行切割，从多孔区域蚀刻材料，或者在多孔区域引导水射流，可以将模具从剩余部分中除去。 在其他实施例中，微特征工件的多孔区域可以接收导电材料以在工件中形成导电路径（例如，线路和/或通孔）。 在另外的实施例中，可以用与工件间隔开的电极和/或支撑电极和工件之间的相对运动来电解形成工件的多孔区域。

    Microfeature workpieces and methods for forming interconnects in microfeature workpieces
    3.
    发明申请
    Microfeature workpieces and methods for forming interconnects in microfeature workpieces 有权
    微型工件和在微型工件中形成互连的方法

    公开(公告)号：US20070045858A1

    公开(公告)日：2007-03-01

    申请号：US11218243

    申请日：2005-09-01

    Applicant: Kyle Kirby ,  William Hiatt ,  Richard Stocks

    Inventor： Kyle Kirby ,  William Hiatt ,  Richard Stocks

    IPC: H01L21/4763 ,  H01L23/48

    CPC classification number: H01L21/76898 ,  H01L21/76868 ,  H01L21/76873 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate of a workpiece. The hole has a first lateral dimension in the dielectric layer and a second lateral dimension in the substrate proximate to an interface between the dielectric layer and the substrate. The second lateral dimension is greater than the first lateral dimension. The method further includes constructing an electrically conductive interconnect in at least a portion of the hole and in electrical contact with the terminal.

    Abstract translation: 在微型工件中形成互连的方法以及具有这种互连的微型工件在此公开。 在一个实施例中，在微特征工件中形成互连的方法包括：将通过端子和电介质层延伸的孔形成在工件的衬底中的至少中间深度。 该孔在电介质层中具有第一横向尺寸，并且该基板中的第二横向尺寸靠近介电层和基底之间的界面。 第二横向尺寸大于第一横向尺寸。 该方法还包括在孔的至少一部分中与端子电接触地构造导电互连。

    Systems and methods for testing microelectronic imagers and microfeature devices
    6.
    发明申请
    Systems and methods for testing microelectronic imagers and microfeature devices 有权
    用于测试微电子成像器和微特征器件的系统和方法

    公开(公告)号：US20060255826A1

    公开(公告)日：2006-11-16

    申请号：US11409060

    申请日：2006-04-24

    Applicant: Salman Akram ,  William Hiatt ,  Alan Wood ,  Charles Watkins ,  Kyle Kirby

    Inventor： Salman Akram ,  William Hiatt ,  Alan Wood ,  Charles Watkins ,  Kyle Kirby

    IPC: G01R31/26

    CPC classification number: G01R31/2635 ,  G01R31/2831

    Abstract: Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.

    Abstract translation: 本文公开了用于测试微电子成像器和微特征器件的系统和方法。 在一个实施例中，一种方法包括提供微功能工件，其包括具有正面，背面和多个微电子管芯的衬底。 各个管芯包括集成电路和在衬底的背面可操作地耦合到集成电路的多个接触焊盘。 该方法包括使各个接触垫与探针卡的相应引脚接触。 该方法还包括测试模具。 在另一个实施例中，各个管芯还可以包括在衬底的前侧的图像传感器，并可操作地耦合到集成电路。 在测试模具时，图像传感器被照亮。

    Image sensor packages and frame structure thereof
    7.
    发明申请
    Image sensor packages and frame structure thereof 有权
    图像传感器封装及其框架结构

    公开(公告)号：US20060192230A1

    公开(公告)日：2006-08-31

    申请号：US11411265

    申请日：2006-04-26

    Applicant: Alan Wood ,  Kyle Kirby ,  Warren Farnworth ,  Salman Akram

    Inventor： Alan Wood ,  Kyle Kirby ,  Warren Farnworth ,  Salman Akram

    IPC: H01L27/148 ,  H01L31/0203

    CPC classification number: H01L27/14618 ,  B33Y80/00 ,  H01L27/14625 ,  H01L2224/48091 ,  H01L2924/00014

    Abstract: A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.

    Abstract translation: 诸如图像传感器封装的半导体封装。 框架结构包括每个具有穿过其中的孔的框架阵列，图像传感器与盖玻片，过滤器，透镜或其它部件组合的模具可以精确相互对准地安装在该框架中。 单片图像传感器骰子和其他组件可以被拾取并放置在框架结构的每个帧中。 或者，框架结构可以被配置为与承载多个图像传感器骰子的晶片对准并且连接到其上，其中沿着框架的周边的任选的向下突出的裙边可以被接收到沿着晶片上的模具位置之间沿着街道切割的切口 ，然后安装其他包装组件。 在任一情况下，将帧结构与单独的图像传感器芯片或连接的晶片组合成单独的图像传感器封装。 可以使用各种外部连接方法。

    Method for fabricating an interconnect for semiconductor components
    8.
    发明申请
    Method for fabricating an interconnect for semiconductor components 失效
    制造半导体元件的互连的方法

    公开(公告)号：US20060181295A1

    公开(公告)日：2006-08-17

    申请号：US11396790

    申请日：2006-04-03

    Applicant: Kyle Kirby

    Inventor： Kyle Kirby

    IPC: G01R31/02

    CPC classification number: G01R1/06711 ,  G01R1/0483 ,  G01R1/07314 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151

    Abstract: A method for fabricating an interconnect for testing a semiconductor component includes the steps of providing a substrate, and forming interconnect contacts on the substrate configured to electrically engage component contacts on the component. The interconnect contacts include flexible spring segments defined by grooves in the substrate, shaped openings in the substrate, or shaped portions of the substrate. The spring segments are configured to flex to exert spring forces on the component contacts, and to compensate for variations in the size or planarity of the component contacts. The interconnect can be configured to test wafer sized components, or to test die sized components.

    Abstract translation: 一种用于制造用于测试半导体部件的互连件的方法包括以下步骤：提供衬底，以及在所述衬底上形成配置成电接合所述部件上的部件触点的互连触点。 互连触点包括由衬底中的凹槽限定的柔性弹簧段，衬底中的成形开口或衬底的成形部分。 弹簧段构造成弯曲以在部件触点上施加弹簧力，并且补偿部件触头的尺寸或平面度的变化。 互连可以配置为测试晶片尺寸的组件，或者测试模具尺寸的组件。

    Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
    9.
    发明申请
    Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements 有权
    衬底，半导体管芯，多芯片模块和包括包括多个导电元件的通孔结构的系统

    公开(公告)号：US20060180941A1

    公开(公告)日：2006-08-17

    申请号：US11405045

    申请日：2006-04-17

    Applicant: Kyle Kirby ,  Warren Farnworth

    Inventor： Kyle Kirby ,  Warren Farnworth

    IPC: H01L23/48

    CPC classification number: B82Y10/00 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1094 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2224/05599 ,  H01L2224/05099

    Abstract: A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hole may be substantially filled with dielectric material, a plurality of smaller, through holes may be formed in the dielectric material, and conductive material may be deposited in the smaller holes. Another method includes forming laterally separated protruding structures in a cavity of a substrate, depositing conductive material over the structures and dielectric material between the structures, and thinning the substrate. Alternatively, conductive nanotubes may be formed in the cavity, and dielectric material may be deposited that surrounds the nanotubes. A method of forming a multichip module includes forming at least one via extending through a plurality of stacked dice that includes a plurality of conductive elements.

    Abstract translation: 形成多导体通孔的方法包括在衬底的至少一个通孔中形成至少一个种子层，选择性地图案化种子层以形成多个横向分离的区域，并在该区域上沉积金属。 或者，通孔可以基本上填充有介电材料，可以在电介质材料中形成多个更小的通孔，并且导电材料可以沉积在较小的孔中。 另一种方法包括在衬底的空腔中形成横向分离的突出结构，在结构之间沉积导电材料并在该结构之间沉积电介质材料，并使衬底变薄。 或者，可以在空腔中形成导电纳米管，并且可以沉积围绕纳米管的电介质材料。 一种形成多芯片模块的方法包括形成至少一个通过包括多个导电元件的多个堆叠的骰子延伸的通孔。

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