公开(公告)号：US06552433B1

公开(公告)日：2003-04-22

申请号：US09858529

申请日：2001-05-17

Applicant: Kuo-Yu Chou ,  Tong-Chern Ong

Inventor： Kuo-Yu Chou ,  Tong-Chern Ong

IPC: H01L2348

CPC classification number: H01L24/05 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/14

Abstract: A vertical structure and a method of forming a vertical structure are disclosed. A partially processed semiconductor wafer is provided having all devise levels completed, including a topmost interlevel dielectric layer through which metallic vias are formed for electrical connection. A first metal level is formed. An IMD level is then formed by forming a blanket dielectric layer over the first metal level, patterning and etching the dielectric layer to form arrays of trenches passing through the dielectric layer, filling the trenches with a conducting material, and performing CMP. A number of metal level, IMD level pairs are formed, where the number could be zero. Bonding metal patterns are deposited, wires are bonded onto the bonding metal patterns and a passivation layer is formed.

Abstract translation: 公开了垂直结构和形成垂直结构的方法。 提供了部分处理的半导体晶片，其具有完成的所有设计水平，包括最顶层的层间电介质层，通过金属通孔形成电气连接。 形成第一金属层。 然后通过在第一金属层上形成覆盖介电层形成IMD电平，对介电层进行构图和蚀刻以形成通过介电层的沟槽阵列，用导电材料填充沟槽，并执行CMP。 形成了多个金属级，IMD级对，其中数字可以为零。 结合金属图案被沉积，导线被接合到接合金属图案上并形成钝化层。

公开(公告)号：US09165968B2

公开(公告)日：2015-10-20

申请号：US13616850

申请日：2012-09-14

Applicant: Calvin Yi-Ping Chao ,  Kuo-Yu Chou ,  Fu-Lung Hsueh

Inventor： Calvin Yi-Ping Chao ,  Kuo-Yu Chou ,  Fu-Lung Hsueh

IPC: H01L27/146 ,  H04N5/374

CPC classification number: H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H04N5/374

Abstract: A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.

Abstract translation: 提供一种堆叠式图像传感器及其制造方法。 堆叠图像传感器包括其上具有像素阵列的上部芯片。 第二芯片包括与像素阵列的列和行相关联的多个列电路和行电路，并且被布置在多个组中的各个列电路和行电路区域中。 在每个芯片上形成芯片间接合焊盘。 在一个实施例中，第二芯片上的芯片间接合焊盘被线性布置并且被包含在列电路区域和行电路区域内。 在其他实施例中，芯片间接合焊盘相对于彼此交错。 在一些实施例中，像素阵列的行和列包括多个信号线，并且相应的列电路区域和行电路区域还包括多个芯片间接合焊盘。

公开(公告)号：US08138804B2

公开(公告)日：2012-03-20

申请号：US12534840

申请日：2009-08-03

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: G11C27/02

CPC classification number: H04N5/378 ,  H04N5/3575

Abstract: A correlated double sampling (CDS) circuit for sampling first and second pixel signals, which are respectively transmitted via first and second data lines, in a pixel array. The CDS circuit includes first and second sampling circuits, an amplifier circuit and a control circuit. The control circuit controls the first sampling circuit to sample a reset level and a data level of the first pixel signal in a first sampling period, and controls the second sampling circuit to sample a reset level and a data level of the second pixel signal in a second sampling period. The control circuit controls the amplifier circuit to output the reset level and the data level of the first pixel signal in a first output period, and output the reset level and the data level of the second pixel signal in a second output period.

Abstract translation: 用于对通过第一和第二数据线分别在像素阵列中发送的第一和第二像素信号进行采样的相关双采样（CDS）电路。 CDS电路包括第一和第二采样电路，放大器电路和控制电路。 所述控制电路控制所述第一采样电路在第一采样周期中对所述第一像素信号的复位电平和数据电平进行采样，并且控制所述第二采样电路对所述第二像素信号的复位电平和数据电平进行采样 第二抽样期。 控制电路控制放大器电路在第一输出周期中输出复位电平和第一像素信号的数据电平，并在第二输出周期中输出第二像素信号的复位电平和数据电平。

公开(公告)号：US20080252364A1

公开(公告)日：2008-10-16

申请号：US11855142

申请日：2007-09-13

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: G05F1/10

CPC classification number: G05F3/24

Abstract: To mitigate kickback noise effect, the present invention provides a reference voltage generator for an analog-to-digital converter circuit. The reference voltage generator includes a bias generator, a bias converter and an output unit. The bias generator is used for generating a first bias voltage in accordance with a reference voltage. The bias converter is coupled to the bias generator and is used for converting the first bias voltage to a second bias voltage. The output unit is coupled to the bias converter and used for generating a first voltage to a load circuit in accordance with the second bias voltage.

Abstract translation: 为了减轻反冲噪声效应，本发明提供了一种用于模数转换器电路的参考电压发生器。 参考电压发生器包括偏置发生器，偏置转换器和输出单元。 偏置发生器用于根据参考电压产生第一偏置电压。 偏置转换器耦合到偏置发生器，并用于将第一偏置电压转换为第二偏置电压。 输出单元耦合到偏置转换器，用于根据第二偏置电压向负载电路产生第一电压。

公开(公告)号：US07312740B2

公开(公告)日：2007-12-25

申请号：US11306256

申请日：2005-12-21

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H03M1/66

CPC classification number: H03M1/68 ,  H03M1/742

Abstract: A current steering digital-to-analog converter (DAC) is provided. At least two lower-resolution DACs are used for converting a high-resolution digital signal. One of the two lower-resolution DACs is used for converting the most significant bits (MSB) of the high-resolution digital signal. The other of the two lower-resolution DACs is used for converting the least significant bits (LSB) of the high-resolution digital signal. By such arrangement, a device mismatch problem is avoided and the chance of variation occurrence during manufacturing process is reduced. The arrangement also simplifies the layout in the significantly scaled-down chip area.

Abstract translation: 提供了一种电流转向数模转换器（DAC）。 至少两个较低分辨率的DAC用于转换高分辨率数字信号。 两个较低分辨率DAC中的一个用于转换高分辨率数字信号的最高有效位（MSB）。 两个较低分辨率DAC中的另一个用于转换高分辨率数字信号的最低有效位（LSB）。 通过这样的布置，避免了器件失配问题，减少了制造过程中发生变化的可能性。 该布置还简化了显着缩小芯片面积的布局。

公开(公告)号：US07280336B2

公开(公告)日：2007-10-09

申请号：US10920309

申请日：2004-08-18

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H02H3/22

CPC classification number: H02H9/04

Abstract: The invention provides a transient voltage detecting circuit for detecting a transient voltage occurring at a power supply or a ground of an electronic system. The circuit according to the invention includes a plurality of detecting units of which the outputs are initially latched by at least one voltage source. The circuit also includes a detecting device outputting a first logic according to the initial outputs of all of the detecting units. When the transient voltage occurs, it is ensured that the logic of the output of one of the detecting units is changed by the transient voltage or the decayed transient voltage, such that the decision device renewably outputs a second logic to trigger a resetting device of the electronic system in accordance with the outputs of all of the detecting units.

Abstract translation: 本发明提供了一种瞬态电压检测电路，用于检测在电子系统的电源或接地处产生的瞬态电压。 根据本发明的电路包括多个检测单元，其中输出端最初由至少一个电压源锁存。 电路还包括根据所有检测单元的初始输出输出第一逻辑的检测装置。 当发生瞬态电压时，确保其中一个检测单元的输出的逻辑由瞬态电压或衰减的瞬态电压改变，使得判定装置可再生地输出第二逻辑以触发复位装置 电子系统根据所有检测单元的输出。

公开(公告)号：US20070090981A1

公开(公告)日：2007-04-26

申请号：US11306256

申请日：2005-12-21

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H03M1/66

CPC classification number: H03M1/68 ,  H03M1/742

Abstract: A current steering digital-to-analog converter (DAC) is provided. At least two lower-resolution DACs are used for converting a high-resolution digital signal. One of the two lower-resolution DACs is used for converting the most significant bits (MSB) of the high-resolution digital signal. The other of the two lower-resolution DACs is used for converting the least significant bits (LSB) of the high-resolution digital signal. By such arrangement, a device mismatch problem is avoided and the chance of variation occurrence during manufacturing process is reduced. The arrangement also simplifies the layout in the significantly scaled-down chip area.

Abstract translation: 提供了一种电流转向数模转换器（DAC）。 至少两个较低分辨率的DAC用于转换高分辨率数字信号。 两个较低分辨率DAC中的一个用于转换高分辨率数字信号的最高有效位（MSB）。 两个较低分辨率DAC中的另一个用于转换高分辨率数字信号的最低有效位（LSB）。 通过这样的布置，避免了器件失配问题，减少了制造过程中发生变化的可能性。 该布置还简化了显着缩小芯片面积的布局。

公开(公告)号：US20060087570A1

公开(公告)日：2006-04-27

申请号：US10905969

申请日：2005-01-28

Applicant: Kuo-Yu Chou ,  Chih-Hua Tsai

Inventor： Kuo-Yu Chou ,  Chih-Hua Tsai

IPC: H04N9/64

CPC classification number: H04N5/367 ,  H04N1/401

Abstract: An image sensing device includes a pixel sensing data processing unit, for receiving a pixel line sensing data to output first and second outputs. A controller receives the first output from the pixel sensing data processing unit, checks whether the pixel line sensing data include at least one defective pixel. If it has defective pixel, a correction rule is applied to compare the status data with a previously defective pixel. The correction rule includes comparing a state data of the previous defect pixels. If the defective pixel belongs to a regular pattern, the defective pixel is not corrected. A correction unit receives the second output and receives the correction status from the controller, and to correct the pixel and exports a display data. A recording unit records the status data of the defective pixel detected by the controller for comparing the status data of the next pixel line sensing data.

Abstract translation: 图像感测装置包括像素感测数据处理单元，用于接收像素线感测数据以输出第一和第二输出。 控制器从像素感测数据处理单元接收第一输出，检查像素线感测数据是否包括至少一个缺陷像素。 如果它具有缺陷像素，则应用校正规则来将状态数据与先前缺陷的像素进行比较。 校正规则包括比较先前缺陷像素的状态数据。 如果缺陷像素属于规则图案，则不校正缺陷像素。 校正单元接收第二输出并从控制器接收校正状态，并校正像素并输出显示数据。 记录单元记录用于比较下一个像素行感测数据的状态数据的控制器检测到的缺陷像素的状态数据。

公开(公告)号：US08350934B2

公开(公告)日：2013-01-08

申请号：US12909154

申请日：2010-10-21

Applicant: Calvin Yi-Ping Chao ,  Honyih Tu ,  Kuo-Yu Chou ,  Po-Sheng Chou

Inventor： Calvin Yi-Ping Chao ,  Honyih Tu ,  Kuo-Yu Chou ,  Po-Sheng Chou

IPC: H04N9/64 ,  H04N17/02

CPC classification number: H04N9/646 ,  H04N5/3572 ,  H04N9/735 ,  H04N17/002

Abstract: An integrated circuit comprises a semiconductor substrate and a color image sensor array on the substrate. The color image sensor array has a first configuration of color pixels for collecting color image data, and at least one crosstalk test pattern on the substrate proximate the color image sensor array. The crosstalk test pattern includes a plurality of color sensing pixels arranged for making color crosstalk measurements. The test pattern configuration is different from the first configuration.

Abstract translation: 集成电路包括在衬底上的半导体衬底和彩色图像传感器阵列。 彩色图像传感器阵列具有用于收集彩色图像数据的彩色像素的第一配置以及靠近彩色图像传感器阵列的基板上的至少一个串扰测试图案。 串扰测试图案包括布置成进行颜色串扰测量的多个颜色感测像素。 测试模式配置与第一种配置不同。

公开(公告)号：US20090244335A1

公开(公告)日：2009-10-01

申请号：US12125914

申请日：2008-05-23

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H04N3/14

CPC classification number: H04N5/2173 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/374 ,  H04N5/378

Abstract: Embodiments of the present invention provide a correlated double sampling (CDS) circuit and a CMOS image sensor unit using the CDS circuit. The CDS circuit shifts levels of sampled sensing signal and reset signal with equal amounts. Thus a voltage difference of the sampled sensing signal and the reset signal remains unchanged, and their levels may fall within a linear input range by adjusting their levels. Compared to a conventional CDS circuit, a gain of the CDS circuit provided by the embodiment of the present invention is not reduced, and thus a design complexity of a rear circuit thereof is lower, and an induced noise is relatively low. Furthermore, the CMOS image sensor unit using the CDS circuit provided by the embodiment also has these advantages.

Abstract translation: 本发明的实施例提供了一种使用CDS电路的相关双采样（CDS）电路和CMOS图像传感器单元。 CDS电路使采样的感测信号和复位信号的电平相等。 因此，采样的感测信号和复位信号的电压差保持不变，并且它们的电平可以通过调整它们的电平而落在线性输入范围内。 与传统的CDS电路相比，本发明实施例提供的CDS电路的增益不会降低，因此其后部电路的设计复杂度较低，并且感应噪声相对较低。 此外，使用本实施例提供的CDS电路的CMOS图像传感器单元也具有这些优点。