公开(公告)号：US06403419B1

公开(公告)日：2002-06-11

申请号：US09717049

申请日：2000-11-22

申请人： Ki Jun Kim ,  Young Ki Shin ,  Byung Soo Park ,  Hee Youl Lee

发明人： Ki Jun Kim ,  Young Ki Shin ,  Byung Soo Park ,  Hee Youl Lee

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

摘要： There is disclosed a method of manufacturing a flash memory device by which an insulating film spacer is formed on both sidewalls of a gate electrode and a drain region is then formed. Thus, the present invention can improve coverage during a deposition process for forming a select gate and reduce the overlapping area of a floating gate and a drain region. Therefore, as the resistance of the select gate itself is reduced depending on the coverage, the present invention can increase the operating speed of a device and can improve the erase characteristic by F-N tunneling due to reduced overlapping area.

摘要翻译： 公开了一种制造闪存器件的方法，通过该方法，在栅电极的两个侧壁上形成绝缘膜间隔物，然后形成漏极区域。 因此，本发明可以改善用于形成选择栅极的沉积工艺中的覆盖，并且减小浮置栅极和漏极区域的重叠面积。 因此，由于根据覆盖范围减小了选择栅极本身的电阻，本发明可以提高器件的工作速度，并且可以通过减少重叠面积的F-N隧穿来提高擦除特性。

公开(公告)号：US20100227469A1

公开(公告)日：2010-09-09

申请号：US12780800

申请日：2010-05-14

申请人： Joo Won Hwang ,  Byung Soo Park ,  Ga Hee Lee

发明人： Joo Won Hwang ,  Byung Soo Park ,  Ga Hee Lee

IPC分类号： H01L21/28

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11541

摘要： A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacture process of high-integrated semiconductor devices. It is therefore possible to minimize an interference phenomenon between neighboring cells. Furthermore, an isolation film is etched after a photoresist film covering only a high-voltage transistor region is formed, or a gate oxide film is formed after a semiconductor substrate is etched at a thickness, which is the same as that of the gate oxide film of the high-voltage transistor region, so that a step between the cell region and the high-voltage transistor region is the same. Accordingly, the coupling ratio can be increased even by the gate oxide film of the high-voltage transistor region, which is thicker than the tunnel oxide film of the cell region. In addition, damage to a tunnel oxide film, a semiconductor substrate or a floating gate while an isolation film is etched at a predetermined depth in order to control the EFH can be prevented by controlling the EFH in such a manner than conductive layer spacers are formed on sidewalls of the floating gate and the isolation film is further etched.

摘要翻译： 一种制造闪速存储器件的方法。 根据本发明，可以形成浮动栅极，并且可以通过使用一个导电层而不使用不能应用于高集成半导体器件的制造工艺的SA-STI工艺来充分确保单元之间的距离。 因此可以使相邻小区之间的干扰现象最小化。 此外，在形成仅覆盖高电压晶体管区域的光致抗蚀剂膜之后蚀刻隔离膜，或者在半导体衬底被蚀刻之后形成栅极氧化膜，其厚度与栅极氧化膜的厚度相同 的高压晶体管区域，使得单元区域和高压晶体管区域之间的台阶相同。 因此，即使通过比电池区域的隧道氧化膜厚的高电压晶体管区域的栅极氧化膜，也可以提高耦合比。 此外，通过以形成导电层间隔物的方式控制EFH，可以防止在以预定深度蚀刻隔离膜以便控制EFH时对隧道氧化物膜，半导体衬底或浮置栅极的损坏 在浮栅的侧壁和隔离膜上被进一步蚀刻。

公开(公告)号：US07358135B2

公开(公告)日：2008-04-15

申请号：US11479147

申请日：2006-06-30

申请人： Byung Soo Park

发明人： Byung Soo Park

IPC分类号： H01L21/336

CPC分类号： H01L28/20 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11526

摘要： A method of forming a resistor of a flash memory device includes etching an isolation structure provided on a semiconductor substrate to form a first trench. A polysilicon structure is formed within the first trench of the isolation structure. A dielectric layer is formed on the polysilicon structure. A polysilicon layer is formed over the dielectric layer. The polysilicon layer is etched to define second and third trenches in the polysilicion layer. The second and third trenches separates the polysilicon layer into first, second, and third sections, where the first and third section contact the polysilicon structure, and the second section is separated from the first and third sections. An insulating film is formed over the etched polysilicion layer, the insulating film filling the second and third trenches. the first section of the polysilicon layer, the polysilicon structure, and the third section of the polysilicon layer define a resistor.

摘要翻译： 形成闪速存储器件的电阻器的方法包括蚀刻设置在半导体衬底上的隔离结构以形成第一沟槽。 在隔离结构的第一沟槽内形成多晶硅结构。 在多晶硅结构上形成介电层。 在电介质层上形成多晶硅层。 蚀刻多晶硅层以在聚硅酸层中限定第二和第三沟槽。 第二和第三沟槽将多晶硅层分离成第一，第二和第三部分，其中第一和第三部分接触多晶硅结构，第二部分与第一和第三部分分离。 在蚀刻的聚硅层上形成绝缘膜，绝缘膜填充第二和第三沟槽。 多晶硅层的第一部分，多晶硅结构和多晶硅层的第三部分限定电阻器。

公开(公告)号：US06777294B2

公开(公告)日：2004-08-17

申请号：US10616715

申请日：2003-07-10

申请人： Byung Soo Park

发明人： Byung Soo Park

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： A method of forming a select line in a NAND type flash memory device is disclosed. In the select line having a stack structure of the floating gate, the dielectric film and the control gate, the control gate is patterned so that a first projection is formed at the edge of the control gate, and the floating gate is formed by means of the self-aligned etch process. At this time, the floating gate is patterned so that a second projection the one end of which overlaps the first projection is formed at the edge of the floating gate. Next, the first and second projections are electrically connected using the contact plugs and the metal line, whereby a voltage is simultaneously applied to the control gate of a low resistance and the floating gate of a high resistance. Therefore, the present invention can minimize generation of voltage drop to improve electrical characteristics, and obviate a process of removing the dielectric film for electrically connecting the floating gate and the control gate to simplify the process steps.

公开(公告)号：US09825047B2

公开(公告)日：2017-11-21

申请号：US13587612

申请日：2012-08-16

申请人： Sung Yoon Cho ,  Hae Jung Lee ,  Byung Soo Park ,  Eun Mi Kim

发明人： Sung Yoon Cho ,  Hae Jung Lee ,  Byung Soo Park ,  Eun Mi Kim

IPC分类号： H01L23/52 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

CPC分类号： H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and having a stepwise pattern, wherein the plurality of word lines each have a pad region, and a plurality of contact plugs coupled to the respective pad regions of the word lines, wherein a width of a pad region of a first one of the plurality of word lines is greater than a width of a pad region of a second word line lower than the first word line.

公开(公告)号：US07662697B2

公开(公告)日：2010-02-16

申请号：US11416738

申请日：2006-05-02

申请人： Jung Ryul Ahn ,  Byung Soo Park

发明人： Jung Ryul Ahn ,  Byung Soo Park

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A method of forming a semiconductor device includes etching a semiconductor substrate to form a first trench having a first width and a first depth; etching the semiconductor substrate to form a second trench having a second width and a second depth, the second trench overlapping the first trench, the second width being greater than the first width, the second depth being less than the first depth, whereby a trench having a dual structure is formed; and forming a first isolation structure within the trench having the dual structure. An embodiment of the present invention relates to a method of forming an isolation structure of a semiconductor device.

摘要翻译： 形成半导体器件的方法包括蚀刻半导体衬底以形成具有第一宽度和第一深度的第一沟槽; 蚀刻所述半导体衬底以形成具有第二宽度和第二深度的第二沟槽，所述第二沟槽与所述第一沟槽重叠，所述第二宽度大于所述第一宽度，所述第二深度小于所述第一深度，由此具有 形成双重结构; 以及在具有双重结构的沟槽内形成第一隔离结构。 本发明的实施例涉及一种形成半导体器件的隔离结构的方法。

公开(公告)号：US20080003762A1

公开(公告)日：2008-01-03

申请号：US11479147

申请日：2006-06-30

申请人： Byung Soo Park

发明人： Byung Soo Park

IPC分类号： H01L21/20

CPC分类号： H01L28/20 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11526

摘要： A method of forming a resistor of a flash memory device includes etching an isolation structure provided on a semiconductor substrate to form a first trench. A polysilicon structure is formed within the first trench of the isolation structure. A dielectric layer is formed on the polysilicon structure. A polysilicon layer is formed over the dielectric layer. The polysilicon layer is etched to define second and third trenches in the polysilicion layer. The second and third trenches separates the polysilicon layer into first, second, and third sections, where the first and third section contact the polysilicon structure, and the second section is separated from the first and third sections. An insulating film is formed over the etched polysilicion layer, the insulating film filling the second and third trenches. the first section of the polysilicon layer, the polysilicon structure, and the third section of the polysilicon layer define a resistor.

公开(公告)号：US07745284B2

公开(公告)日：2010-06-29

申请号：US11500594

申请日：2006-08-08

申请人： Joo Won Hwang ,  Byung Soo Park ,  Ga Hee Lee

发明人： Joo Won Hwang ,  Byung Soo Park ,  Ga Hee Lee

IPC分类号： H01L21/363

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11541

摘要： A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacturing process of highly integrated semiconductor devices. It is therefore possible to minimize interference between neighboring cells.

摘要翻译： 一种制造闪速存储器件的方法。 根据本发明，可以形成浮动栅极，并且可以通过使用一个导电层而不使用不能应用于高度集成的半导体器件的制造工艺的SA-STI工艺来充分确保单元之间的距离。 因此可以最小化相邻小区之间的干扰。

公开(公告)号：US20070275531A1

公开(公告)日：2007-11-29

申请号：US11618709

申请日：2006-12-29

申请人： Byung Soo Park

发明人： Byung Soo Park

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of manufacturing a flash memory device includes forming a gate over a semiconductor substrate in which a cell region, a low voltage region and a high voltage region are defined. First ions are implanted into the cell region to form doped junctions in the cell region, the low voltage region and the high voltage region being covered to prevent the first ions from being implanted into the low voltage region and the high voltage region. The first ions implanted into the cell region are activated using a rapid annealing process. The rapid annealing process is performed for no more than 10 minutes. The rapid annealing process minimizes an occurrence of Transient Enhanced Diffusion at the cell region.

摘要翻译： 制造闪速存储器件的方法包括在半导体衬底上形成栅极，其中限定了单元区域，低电压区域和高电压区域。 将第一离子注入到单元区域中以在单元区域中形成掺杂结，覆盖低电压区域和高电压区域以防止第一离子注入低电压区域和高电压区域。 使用快速退火工艺激活注入细胞区域的第一离子。 快速退火处理不超过10分钟。 快速退火过程最小化细胞区域瞬态增强扩散的发生。

公开(公告)号：US06960805B2

公开(公告)日：2005-11-01

申请号：US10750850

申请日：2004-01-05

申请人： Byung Jin Ahn ,  Byung Soo Park ,  Sung Jae Chung

发明人： Byung Jin Ahn ,  Byung Soo Park ,  Sung Jae Chung

IPC分类号： G11C16/02 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203

摘要： The present invention relates to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell. According to the present invention, a source region and a drain region are first formed and a tunnel oxide film is then formed. Therefore, it is possible to prevent damage of the tunnel oxide film due to an ion implantation process. Further, independent two channel regions are formed below the floating gate. Thus, it is possible to store data of two or more bits at a single cell. In addition, the tunnel oxide film, the floating gate and the dielectric film having an ONO structure are formed at a given regions. It is thus possible to reduce the steps of a process and improve an electrical characteristic and integration level of a device.

摘要翻译： 本发明涉及一种闪存单元及其制造方法，以及闪存单元中的编程/擦除/读取方法。 根据本发明，首先形成源极区域和漏极区域，然后形成隧道氧化膜。 因此，可以防止由于离子注入工艺而引起的隧道氧化膜的损坏。 此外，在浮动栅极下方形成独立的两个沟道区域。 因此，可以在单个单元存储两个或多个位的数据。 此外，隧道氧化物膜，浮栅和具有ONO结构的电介质膜形成在给定的区域。 因此，可以减少处理的步骤并提高装置的电气特性和集成度。