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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08604544B2

    公开(公告)日：2013-12-10

    申请号：US13049540

    申请日：2011-03-16

    申请人： Kenichi Matsushita

    发明人： Kenichi Matsushita

    IPC分类号： H01L29/66

    CPC分类号： H01L27/0623 ,  H01L29/1095 ,  H01L29/7397

    摘要： According to one embodiment, a semiconductor device includes a first main electrode, a base layer of a first conductivity type, a barrier layer of the first conductivity type, a diffusion layer of a second conductivity type, a base layer of the second conductivity type, a first conductor layer, a second conductor layer, and a second main electrode. Bottoms of the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are positioned on the first main electrode side of lower ends of the first conductor layer and the second conductor layer. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type form a super junction proximally to tips of the first conductor layer and the second conductor layer.

    摘要翻译： 根据一个实施例，半导体器件包括第一主电极，第一导电类型的基极层，第一导电类型的势垒层，第二导电类型的扩散层，第二导电类型的基极层， 第一导体层，第二导体层和第二主电极。 第一导电类型的阻挡层的底部和第二导电类型的扩散层位于第一导体层和第二导体层的下端的第一主电极侧上。 第一导电类型的阻挡层和第二导电类型的扩散层形成与第一导体层和第二导体层的尖端近端的超级结。

    SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR FOR USE AS A HIGH-SPEED SWITCHING DEVICE AND A POWER DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR FOR USE AS A HIGH-SPEED SWITCHING DEVICE AND A POWER DEVICE 有权
    包括用作高速开关器件和功率器件的场效应晶体管的半导体器件

    公开(公告)号：US20100096696A1

    公开(公告)日：2010-04-22

    申请号：US12645072

    申请日：2009-12-22

    申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

    发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

    摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

    摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

    Semiconductor device used as high-speed switching device and power device
    3.
    发明授权
    Semiconductor device used as high-speed switching device and power device 失效
    半导体器件用作高速开关器件和功率器件

    公开(公告)号：US07692242B2

    公开(公告)日：2010-04-06

    申请号：US11505337

    申请日：2006-08-17

    申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

    发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

    IPC分类号： H01L29/04 ,  H01L29/06

    CPC分类号： H01L29/1045 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7838

    摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

    摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

    INTEGRATED CIRCUIT DEVICE
    7.
    发明申请
    INTEGRATED CIRCUIT DEVICE 失效
    集成电路设备

    公开(公告)号：US20090128279A1

    公开(公告)日：2009-05-21

    申请号：US12269396

    申请日：2008-11-12

    申请人： Kenichi Matsushita ,  Ichiro Omura

    发明人： Kenichi Matsushita ,  Ichiro Omura

    IPC分类号： G05F1/00 ,  H01F27/28

    CPC分类号： H01F17/0033 ,  H01F27/402 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit device includes: a main interconnect; and a coil located on one side of the main interconnect at a position fixed with respect to the main interconnect, the coil having a central axis extending in a direction crossing the extending direction of the main interconnect. An induction current detectable by the coil is generated due to a current flowing through the main interconnect.

    摘要翻译： 集成电路装置包括：主互连; 以及位于所述主互连的一侧上的线圈，所述线圈相对于所述主互连固定，所述线圈具有沿与所述主互连的延伸方向交叉的方向延伸的中心轴线。 由于电流流过主互连线，可以产生由线圈检测到的感应电流。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20080251838A1

    公开(公告)日：2008-10-16

    申请号：US12118159

    申请日：2008-05-09

    申请人： Syotaro Ono ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Norio Yasuhara ,  Kenichi Matsushita ,  Shinichi Hodama ,  Akio Nakagawa

    发明人： Syotaro Ono ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Norio Yasuhara ,  Kenichi Matsushita ,  Shinichi Hodama ,  Akio Nakagawa

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7809

    摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.

    摘要翻译： 半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部 并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上， 以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。

    Semiconductor device including field effect transistor for use as a high-speed switching device and a power device
    10.
    发明申请
    Semiconductor device including field effect transistor for use as a high-speed switching device and a power device 失效
    包括用作高速开关装置的场效应晶体管和功率器件的半导体装置

    公开(公告)号：US20070034894A1

    公开(公告)日：2007-02-15

    申请号：US11501715

    申请日：2006-08-10

    申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

    发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

    IPC分类号： H01L29/74

    CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

    摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

    摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。