公开(公告)号：US07085794B2

公开(公告)日：2006-08-01

申请号：US10122997

申请日：2002-04-12

申请人： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

发明人： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

IPC分类号： G06F7/38 ,  G06F17/10

CPC分类号： G06F7/5443 ,  G06F7/49994 ,  H03H17/0233 ,  H03H17/06

摘要： An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

公开(公告)号：US07328227B2

公开(公告)日：2008-02-05

申请号：US11359201

申请日：2006-02-22

申请人： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

发明人： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

IPC分类号： G06F7/00

CPC分类号： G06F7/5443 ,  G06F7/49994 ,  H03H17/0233 ,  H03H17/06

摘要： An low power vector summation apparatus is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

摘要翻译： 提供了一种低功率矢量求和装置，用于使用2的补码运算而没有现有技术的高切换活动。 特别地，本发明操作以利用2的补码的符号扩展属性。 提供2的补码减少的表示，以避免符号扩展和符号扩展位的切换。 检测2的补码的最大幅度，并动态生成其缩小表示以表示信号。 通过缩小表示引入的恒定误差也被动态补偿。

公开(公告)号：US20060143259A1

公开(公告)日：2006-06-29

申请号：US11359201

申请日：2006-02-22

申请人： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

发明人： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

IPC分类号： G06F7/38

CPC分类号： G06F7/5443 ,  G06F7/49994 ,  H03H17/0233 ,  H03H17/06

摘要： An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

公开(公告)号：US09100228B2

公开(公告)日：2015-08-04

申请号：US12907435

申请日：2010-10-19

申请人： Samer Hijazi ,  Kameran Azadet ,  Meng-Lin Yu ,  Joseph Othmer ,  Ramon Sanchez Perez

发明人： Samer Hijazi ,  Kameran Azadet ,  Meng-Lin Yu ,  Joseph Othmer ,  Ramon Sanchez Perez

IPC分类号： H04B17/00 ,  H04L25/02

CPC分类号： H04L25/0232 ,  H04L25/0212 ,  H04L25/0226

摘要： A method and system for canonical channel estimation in the Long Term Evolution uplink where a multi-frequency signal is generated and then converted to frequency spectrum which is then convolved in the frequency domain with a truncated window function to obtain a time domain channel impulse response. The time domain channel impulse response can be then transformed to a frequency domain to produce a down sampled user channel response, which can be then linearly interpolated to provide a channel estimate for a plurality of subcarriers. Such an approach achieves channel estimation within Long Term Evolution at only canonical locations to reduce complexity without loss in channel entropy.

摘要翻译： 一种用于在长期演进上行链路中进行规范信道估计的方法和系统，其中生成多频信号，然后将其转换为频谱，然后将频谱卷积在具有截断窗函数的频域中以获得时域信道脉冲响应。 然后可以将时域信道脉冲响应变换到频域以产生下采样的用户信道响应，然后可以对其进行线性内插以提供多个子载波的信道估计。 这种方法在长期演进中仅在规范位置实现信道估计，以减少复杂度而不损失信道熵。

公开(公告)号：US20140108477A1

公开(公告)日：2014-04-17

申请号：US13701376

申请日：2012-10-26

申请人： Kameran Azadet ,  Meng-Lin Yu ,  Joseph H. Othmer ,  Joseph Williams ,  Albert Molina

发明人： Kameran Azadet ,  Meng-Lin Yu ,  Joseph H. Othmer ,  Joseph Williams ,  Albert Molina

IPC分类号： G06F5/01

CPC分类号： G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

摘要： A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises Ni samples; and performing a weighted sum of the time shifted versions of the vector by a vector of Ni coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

摘要翻译： 提供了具有具有向量卷积函数的指令集的向量处理器。 所公开的向量处理器通过获得包括至少N1 + N2-1个输入样本的向量来执行输入信号和滤波器脉冲响应之间的卷积函数; 获得矢量的N2时移版本（包括零位版本），其中每个时移版本包括Ni样本; 以及通过Ni系数的向量来执行向量的时移版本的加权和; 以及产生包括每个加权和的一个输出值的输出向量。 矢量处理器例如响应于具有矢量输入的一个或多个向量卷积软件指令来执行该方法。 矢量可以包括多个实数或复数输入样本，并且可以使用实数或复数的多个系数来表示滤波器脉冲响应。

公开(公告)号：US06192072B1

公开(公告)日：2001-02-20

申请号：US09326781

申请日：1999-06-04

申请人： Kameran Azadet ,  Meng-Lin Yu

发明人： Kameran Azadet ,  Meng-Lin Yu

IPC分类号： H03H730

CPC分类号： H04L25/03057 ,  H04L2025/0349

摘要： A method and apparatus are disclosed for increasing the effective processing speed of a parallel decision-feedback equalizer (DFE) by combining block processing and look-ahead techniques in the selection (multiplexing) stage. The present invention extends a parallel DFE by using look-ahead techniques in the selection stage to precompute the effect of previous blocks on each subsequent block, and to thereby remove the serial output dependency. The parallel DFE includes a multiplexor tree structure that selects an appropriate output value for each block and precomputes the effect of previous blocks on each subsequent block. A multiplexing delay algorithm on the order of logN is employed to resolve the output dependency and thus speeds up parallel block processing DFEs. The disclosed DFE architecture can be combined with pipelining to completely eliminate the critical path problem. Pipelining reduces the required critical path timing to one multiplexing time. The disclosed multiplexor tree circuitry for the parallel DFE groups multiplexor blocks into groups of two, referred to as block pairs, and provides at least one multiplexor for each block, i, to select an output value, yi, from among the possible precomputed values. The output of each parallel block depends on the possible precomputed values generated by the look-ahead processors for the block, as well as the actual values that are ultimately selected for each previous block. In order to reduce the delay in obtaining each actual output value, the present invention assumes that each block contains each possible value, and carries the assumption through to all subsequent blocks. Thus, the number of multiplexors required to select from among the possible values grows according to N·logN, where N is the block number.

摘要翻译： 公开了一种用于通过在选择（复用）阶段中组合块处理和先行技术来增加并行判决反馈均衡器（DFE）的有效处理速度的方法和装置。 本发明通过在选择阶段中使用先行技术来扩展并行DFE，以预先计算先前块对每个后续块的影响，从而消除串行输出依赖性。 并行DFE包括多路复用器树结构，其为每个块选择适当的输出值，并且预先计算先前块在每个后续块上的影响。 采用logN顺序的复用延迟算法来解决输出依赖关系，从而加快并行块处理DFE。 所公开的DFE架构可以与流水线结合，以完全消除关键路径问题。 流水线将所需的关键路径时序减少到一个复用时间。 所公开的用于并行DFE组多路复用器的多路复用器树电路块分成两组，被称为块对，并且为每个块提供至少一个多路复用器，i从可能的预计算值中选择输出值yi。 每个并行块的输出取决于由块的先行处理器生成的可能的预计算值，以及最终为每个先前块选择的实际值。 为了减少获得每个实际输出值的延迟，本发明假设每个块包含每个可能的值，并将假设传递给所有后续块。 因此，从可能值中选择的多路复用器的数量根据N.logN而增长，其中N是块号。

公开(公告)号：US09170776B2

公开(公告)日：2015-10-27

申请号：US12362899

申请日：2009-01-30

申请人： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

发明人： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC分类号： G06F1/035 ,  G06F7/556 ,  G06F1/03

CPC分类号： G06F7/556 ,  G06F1/0307 ,  G06F1/035 ,  G06F2101/10

摘要： A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table. The disclosed digital signal processor evaluates a logarithm function for an input value, x, by decomposing the input value, x, to a first part, N, a second part, q, and a remaining part, r, wherein the first part, N, is identified by a position of a most significant bit of the input value, x, and the second part, q, is comprised of a number of bits following the most significant bit, wherein the number is small relative to a number of bits in the input value, x; obtaining a value Log 2 ⁡ ( 1 + 1 2 ⁢ q ) from a first look-up table based on the second part, q; computing an epsilon term, ε, using the expression 2 - N 1 + 1 2 ⁢ q ⁢ r ; evaluating an expression Log2 (1+ε) using a polynomial approximation, such as a cubic approximation; and determining the logarithm function for the input value, x, by summing the values of N, Log Z ⁡ ( 1 + 1 2 ⁢ q ) and Log2(1+ε).

摘要翻译： 提供一种数字信号处理器，其具有使用缩减的查找表的具有对数函数的指令集。 所公开的数字信号处理器通过将输入值x分解为第一部分N，第二部分q和剩余部分r来评估输入值x的对数函数，其中第一部分N 由输入值x的最高有效位的位置识别，第二部分q由最高有效位之后的位数组成，其中该数目相对于位数 输入值x; 基于第二部分从第一查找表获得值Log 2⁡（1 + 1 2 q）q; 使用表达式2-N 1 + 1 2 q r;计算ε项，＆egr; 使用诸如立方近似的多项式近似来评估表达式Log2（1 +＆egr;）; 并且通过将N，Log Z⁡（1 + 1 2 q）和Log2（1 +＆egr））的值求和来确定输入值x的对数函数。

公开(公告)号：US08799341B2

公开(公告)日：2014-08-05

申请号：US11781313

申请日：2007-07-23

申请人： Kameran Azadet

发明人： Kameran Azadet

IPC分类号： G06F17/10

CPC分类号： H03H17/06 ,  H03F1/32 ,  H03H2017/0692 ,  H03H2218/06

摘要： Multi-dimensional finite impulse response filters ale disclosed in hybrid and transpose forms. Multi-dimensional signals can be expressed in a vector (ox matrix) form to allow multi-dimensional signals to be processed collectively. Known hybrid and transpose FIR filters are extended to the multi-dimensional case to allow multi-dimensional signals to be processed with reduced redundancies. The input signals are vectors with multidimensional components. The disclosed FIR filters include multipliers that perform matrix multiplications with multiple coefficients, and adders for performing vector additions with multiple inputs and outputs. The z-transforms are provided for the disclosed hybrid and transpose multi-dimensional FIR filters.

摘要翻译： 混合和转置形式中公开的多维有限脉冲响应滤波器。 多维信号可以以向量（ox矩阵）形式表示，以允许集体处理多维信号。 已知的混合和转置FIR滤波器被扩展到多维情况，以允许以减少的冗余来处理多维信号。 输入信号是具有多维分量的向量。 所公开的FIR滤波器包括执行具有多个系数的矩阵乘法的乘法器和用于执行具有多个输入和输出的矢量加法的加法器。 为所公开的混合和转置多维FIR滤波器提供z变换。

公开(公告)号：US08635516B2

公开(公告)日：2014-01-21

申请号：US13302707

申请日：2011-11-22

申请人： Kameran Azadet ,  Erich F. Haratsch

发明人： Kameran Azadet ,  Erich F. Haratsch

IPC分类号： H03M13/03

CPC分类号： H04L25/03006 ,  H03M13/256 ,  H03M13/39 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/6331 ,  H04L25/03305

摘要： A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols and subtracts the intersymbol interference from the received signal. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol.

摘要翻译： 公开了一种用于执行在多个符号持续时间上发送的多维码的联合均衡和解码的方法和装置。 公开了一种RSSE方案，其消除由同一多维码符号内的其他符号分量引起的内部符号干扰。 所披露的用于多维码的RSSE技术适用于网格码数量超过信道数量的地方。 所公开的RSSE解码器计算由先前解码的多维码符号引起的符号间干扰，并从接收信号中减去符号间干扰。 此外，分支度量单元补偿由相同的多维码符号内的其他符号分量引起的内部符号干扰。

公开(公告)号：US20130080855A1

公开(公告)日：2013-03-28

申请号：US13247439

申请日：2011-09-28

申请人： Samer Hijazi ,  Carl Murray ,  Joseph H. Othmer ,  Albert Molina ,  Kameran Azadet

发明人： Samer Hijazi ,  Carl Murray ,  Joseph H. Othmer ,  Albert Molina ,  Kameran Azadet

IPC分类号： H03M13/13 ,  G06F11/10

CPC分类号： H03M13/451 ,  H03M13/13 ,  H03M13/6502

摘要： A search sphere-based linear block decoder is provided. A received vector, v, is decoded by computing a syndrome vector, S, corresponding to the received vector, v; (S=vH); obtaining a set of all possible error vectors, e, corresponding to the computed syndrome vector, S, wherein the set of all possible error vectors, e, is obtained from a pre-computed error table and has a specified maximum number of bit errors; calculating a set of all possible received vectors, x, based on the received vector, v, and the set of all possible error vectors, e; determining a k-bit code-vector x that is closest to the received vector, v; and determining an n-bit data-vector, d, associated with the k-bit code-vector x. The pre-computed error table can be generated by multiplying all possible error vectors by a Syndrome Matrix, to obtain all possible syndrome vectors associated with all possible error vectors.

摘要翻译： 提供基于搜索范围的线性块解码器。 通过计算对应于接收向量v的校正子向量S来解码接收向量v， （S = vH）; 获得对应于所计算的校正子向量S的所有可能的误差向量集合，其中所有可能的误差向量集合e从预先计算的误差表获得并且具有指定的最大数量的比特错误; 基于所接收的向量v和所有可能的误差向量的集合e来计算所有可能的接收向量x的集合; 确定最接近接收矢量的k位码矢量，v; 以及确定与所述k位码矢量x相关联的n位数据矢量d。 可以通过将所有可能的误差向量乘以综合征矩阵来产生预计算误差表，以获得与所有可能的误差向量相关联的所有可能的校正子向量。