- 专利标题: Low power vector summation method and apparatus
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申请号: US10122997申请日: 2002-04-12
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公开(公告)号: US07085794B2公开(公告)日: 2006-08-01
- 发明人: Kameran Azadet , Meng-Lin Yu , Zhan Yu
- 申请人: Kameran Azadet , Meng-Lin Yu , Zhan Yu
- 申请人地址: US PA Allentown
- 专利权人: Agere Systems Inc.
- 当前专利权人: Agere Systems Inc.
- 当前专利权人地址: US PA Allentown
- 主分类号: G06F7/38
- IPC分类号: G06F7/38 ; G06F17/10
摘要:
An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.
公开/授权文献
- US20030195906A1 Low power vector summation method and apparatus 公开/授权日:2003-10-16
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