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公开(公告)号：US11838028B2
公开(公告)日：2023-12-05
申请号：US17687110
申请日：2022-03-04
Inventor： SeongHwan Cho , Junseok Hong , Pangi Park
CPC classification number: H03M1/1215 , H03M1/1245
Abstract: The present disclosure discloses a band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO) including a first converter configured to receive an analog input signal and quantize the analog input signal according to a first clock signal to output a first digital signal, a second converter configured to receive the analog input signal and quantize the analog input signal in a time-interleaving manner according to a second clock signal, which has a phase opposite to that of the first clock signal, to output a second digital signal, and a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal.
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公开(公告)号：US11379187B2
公开(公告)日：2022-07-05
申请号：US16834706
申请日：2020-03-30
Inventor： Jin-O Seo , Hyuk-Jin Lee , SeongHwan Cho
IPC: G06F7/544 , G06F7/523 , G11C11/4096 , G06N3/04
Abstract: A semiconductor device includes a cell array, a computation circuit, and a control circuit. The cell array includes a plurality of unit cells configured to store a plurality of first signals by a write operation and to output a plurality of output signals corresponding to the first signals by a read operation. The computation circuit includes a plurality of unit computation circuits receiving the plurality of output signals and being set according to a plurality of second signals during a computation operation. The control circuit is configured to control the cell array and the computation circuit during the write operation, the read operation, and the computation operation.
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公开(公告)号：US09490788B2
公开(公告)日：2016-11-08
申请号：US14856432
申请日：2015-09-16
Inventor： Yong-Jo Kim , SeongHwan Cho
CPC classification number: H03K5/135 , H03K2005/00019 , H03L7/0814
Abstract: A semiconductor device includes a first variable delay circuit that delays inputted multiphase signals according to a delay control signal, a selection circuit that selects and outputs two signals of signals output from the first variable delay circuit, a second variable delay circuit that delays one of the two signals according to the delay control signal, a phase comparison circuit that compares a phase of a signal outputted by the second variable delay circuit with a phase of the other of the two signals, a filter that updates the delay control signal according to a signal outputted by the phase comparison circuit, and a delay control signal selection circuit that provides the delay control signal to the first variable delay circuit or the second variable delay circuit.
Abstract translation: 一种半导体器件包括：第一可变延迟电路，其根据延迟控制信号延迟输入的多相信号;选择电路，选择和输出从第一可变延迟电路输出的信号的两个信号;第二可变延迟电路， 根据所述延迟控制信号的两个信号;相位比较电路，其将由所述第二可变延迟电路输出的信号的相位与所述两个信号中的另一个的相位进行比较;滤波器，其根据信号更新所述延迟控制信号 由相位比较电路输出的延迟控制信号选择电路和向第一可变延迟电路或第二可变延迟电路提供延迟控制信号的延迟控制信号选择电路。
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Patent Agency Ranking
公开(公告)号：US11526739B2
公开(公告)日：2022-12-13
申请号：US16838916
申请日：2020-04-02
Inventor： Jin-O Seo , Hyuk-Jin Lee , SeongHwan Cho
Abstract: A nonvolatile memory device includes a memory cell array and an computation output circuit. The memory cell array includes a plurality of nonvolatile memory elements configured to store a plurality of weights respectively and a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals. The computation output circuit is configured to generate a computation signal from voltages induced at the plurality of bit lines according to the plurality of input signals.
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公开(公告)号：US10566961B2
公开(公告)日：2020-02-18
申请号：US16279719
申请日：2019-02-19
Inventor： Seonggyu Lee , Yongjo Kim , SeongHwan Cho
Abstract: A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.
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公开(公告)号：US10250243B2
公开(公告)日：2019-04-02
申请号：US15658272
申请日：2017-07-24
Inventor： Seonggyu Lee , Yongjo Kim , SeongHwan Cho
Abstract: A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.
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公开(公告)号：US11881243B2
公开(公告)日：2024-01-23
申请号：US17524447
申请日：2021-11-11
Inventor： Kyunghyun Kim , Jino Seo , Hyukjin Lee , SeongHwan Cho
CPC classification number: G11C11/40 , G06F7/50 , G06F7/523 , G06F7/5443 , H03M1/74
Abstract: A semiconductor device includes a memory cell array including a plurality of memory cells coupled between a multiplicity of word lines and one or more bit lines; and an operation circuit configured to perform a multiplication and accumulation (MAC) operation with one or more first multi-bit data provided from the one or more bit lines and one or more second multi-bit data, wherein a plurality of memory cells coupled to a bit line store a plurality of bits included in a corresponding one of the one or more first multi-bit data, and wherein the memory cell array sequentially provides the plurality of bits included in the corresponding first multi-bit data to the operation circuit.
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公开(公告)号：US20220376697A1
公开(公告)日：2022-11-24
申请号：US17687110
申请日：2022-03-04
Inventor： SeongHwan Cho , Junseok Hong , Pangi Park
IPC: H03M1/12
Abstract: The present disclosure discloses a band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO) including a first converter configured to receive an analog input signal and quantize the analog input signal according to a first clock signal to output a first digital signal, a second converter configured to receive the analog input signal and quantize the analog input signal in a time-interleaving manner according to a second clock signal, which has a phase opposite to that of the first clock signal, to output a second digital signal, and a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal.
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