公开(公告)号：US10566961B2

公开(公告)日：2020-02-18

申请号：US16279719

申请日：2019-02-19

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Seonggyu Lee ,  Yongjo Kim ,  SeongHwan Cho

IPC: H03K5/00 ,  H03K5/15

Abstract: A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.

公开(公告)号：US10250243B2

公开(公告)日：2019-04-02

申请号：US15658272

申请日：2017-07-24

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Seonggyu Lee ,  Yongjo Kim ,  SeongHwan Cho

IPC: H03K5/00 ,  H03K5/15

Abstract: A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.