公开(公告)号：US09252027B1

公开(公告)日：2016-02-02

申请号：US14644880

申请日：2015-03-11

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yusuke Kasahara ,  Kei Kobayashi

IPC: H01L21/31 ,  H01L21/475 ,  H01L21/02

CPC classification number: H01L21/0337

Abstract: In accordance with an embodiment, a method of forming a pattern includes forming a first layer on a fabrication target film, making a mold and the first layer push each other to form a protrusion on the fabrication target film, and forming first and second regions, forming a block copolymer layer including first and second blocks in the first and second regions, phase-separating the block copolymer layer, forming second and third layers in the first region, and forming fourth and fifth layers in the second region; and removing the third and fifth layers. The first region is surrounded by the first layer and the protrusion. The second region is surrounded by the first layer and contacts the first region via the protrusion. The third layer is surrounded by the second layer. The fifth layer is surrounded by the fourth layer.

Abstract translation: 根据实施例，形成图案的方法包括在制造目标薄膜上形成第一层，制造模具并且第一层彼此推动以在制造目标薄膜上形成突起，并且形成第一和第二区域， 在所述第一和第二区域中形成包含第一和第二嵌段的嵌段共聚物层，相分离所述嵌段共聚物层，在所述第一区域中形成第二和第三层，并在所述第二区域中形成第四和第五层; 并移除第三层和第五层。 第一区域被第一层和突起包围。 第二区域被第一层包围，并经由突起与第一区域接触。 第三层被第二层包围。 第五层被第四层包围。

公开(公告)号：US09685331B1

公开(公告)日：2017-06-20

申请号：US15231393

申请日：2016-08-08

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Ayako Kawanishi ,  Yusuke Kasahara ,  Hiroki Yonemitsu

IPC: H01L21/02 ,  H01L21/32 ,  H01L21/027 ,  H01L21/324 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/0274 ,  G03F7/0002 ,  G03F7/162 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/324

Abstract: A semiconductor device manufacturing method includes forming a first film on a substrate having a first region and a second region. A second film is formed on the first film. Guide grooves are formed by removing portions of the second film and exposing the first film. A self-assembly material is coated on the exposed first film and heated to cause a phase separation into a first and a second phase section. The self-assembly material is irradiated. A mask pattern including at least a portion of the first phase section is formed by removing the second phase section. The mask pattern has a first dimension in the first region and a second dimension in the second region that is different from the first dimension. The first film is etched after the mask pattern is formed.

公开(公告)号：US09029266B2

公开(公告)日：2015-05-12

申请号：US13971922

申请日：2013-08-21

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yusuke Kasahara ,  Noriko Sakurai

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/115

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11556 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor device manufacturing method includes depositing a silicon film above a semiconductor substrate, forming an insulating film which includes silicon oxide or silicon nitride on the silicon film, forming a physical guide having a depressed portion above the insulating film, forming a directed self-assembly material layer which includes a first polymer and a second polymer in the depressed portion of the physical guide, phase-separating the directed self-assembly material layer into a first region which includes the first polymer and a second region which includes the second polymer, removing the second region, processing the insulating film by using the physical guide and the first region as masks, and transferring a pattern corresponding to the second region to the insulating film. Further, the silicon film is processed by using the pattern transferred onto the insulating film as a mask.

Abstract translation: 根据一个实施例，半导体器件制造方法包括在半导体衬底上沉积硅膜，在硅膜上形成包括氧化硅或氮化硅的绝缘膜，形成在绝缘膜上方具有凹陷部分的物理引导件，形成 定向自组装材料层，其在物理引导件的凹陷部分中包括第一聚合物和第二聚合物，将定向的自组装材料层相分离成包括第一聚合物的第一区域和包括第一聚合物的第二区域， 第二聚合物，去除第二区域，通过使用物理引导件和第一区域作为掩模来处理绝缘膜，并将与第二区域相对应的图案转印到绝缘膜。 此外，通过使用转印到绝缘膜上的图案作为掩模来处理硅膜。

公开(公告)号：US09696628B2

公开(公告)日：2017-07-04

申请号：US15067951

申请日：2016-03-11

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yusuke Kasahara ,  Hideki Kanai

IPC: G03F7/40 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/02 ,  G03F7/00 ,  H01L21/311 ,  B81C1/00 ,  G03F7/16 ,  G03F7/11 ,  G03F7/20 ,  H01L21/033

CPC classification number: G03F7/40 ,  B81C1/00031 ,  B81C2201/0149 ,  G03F7/0002 ,  G03F7/002 ,  G03F7/0035 ,  G03F7/11 ,  G03F7/165 ,  G03F7/2016 ,  H01L21/02118 ,  H01L21/02318 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/31058 ,  H01L21/31144

Abstract: According to one embodiment, a pattern forming method includes forming a resist pattern on an under-layer, forming a recessed portion in the under-layer by etching the under-layer using the resist pattern as a mask, slimming the resist pattern, forming a neutral layer having an affinity for first and second polymers on a region of the under-layer not covered with the slimmed resist pattern, forming a block copolymer film containing the first polymer and the second polymer on the slimmed resist pattern and the neutral layer, and forming a microphase separation pattern comprising a first portion formed of the first polymer and a second portion formed of the second polymer by applying microphase separation processing to the block copolymer film.

公开(公告)号：US09371427B2

公开(公告)日：2016-06-21

申请号：US14636034

申请日：2015-03-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Katsutoshi Kobayashi ,  Yusuke Kasahara ,  Hiroki Yonemitsu ,  Hitoshi Kubota ,  Ayako Kawanishi

IPC: C23F1/00 ,  C08J7/00 ,  B81C1/00 ,  C23F4/00

CPC classification number: C23F1/00 ,  B81C1/00396 ,  C23F4/00 ,  G03F7/0002

Abstract: A pattern is formed by forming a first pattern on a first film, forming a block copolymer layer including a first block chain and a second block chain on the first pattern, forming a second pattern, forming a second film on the second pattern, selectively removing the second film until the second pattern is exposed, forming a third pattern, and processing the first film using the third pattern as a mask. The second pattern is formed by microphase-separating the block copolymer layer, and removing the first block chain or the second block chain. The second film is formed by applying a material having an etch rate that is less than an etch rate of a material of the first pattern and the second pattern. The third pattern is formed by selectively removing the second pattern and the first pattern using the second film as a mask.

Abstract translation: 通过在第一膜上形成第一图案形成图案，在第一图案上形成包含第一嵌段链和第二嵌段链的嵌段共聚物层，形成第二图案，在第二图案上形成第二膜，选择性地除去 直到第二图案曝光的第二膜，形成第三图案，并且使用第三图案作为掩模来处理第一膜。 第二图案通过微相分离嵌段共聚物层并除去第一嵌段链或第二嵌段链形成。 通过施加具有小于第一图案和第二图案的材料的蚀刻速率的蚀刻速率的材料来形成第二膜。 通过使用第二膜作为掩模选择性地去除第二图案和第一图案来形成第三图案。

公开(公告)号：US20150151329A1

公开(公告)日：2015-06-04

申请号：US14191869

申请日：2014-02-27

Applicant: Kabushiki Kaisha Toshiba

Inventor： Ayako KAWANISHI ,  Hirokazu Kato ,  Hiroki Yonemitsu ,  Yusuke Kasahara

IPC: B05D7/00 ,  B05D3/06

CPC classification number: G03F7/0002

Abstract: In a pattern forming method according to the present embodiment, a first guide layer having a first pattern is formed above a base material. A second guide layer having a second pattern intersecting the first pattern is formed. A directed self-assembly material is introduced in a concave portion surrounded by the first and second guide layers. A directed self-assembly pattern having a diameter which is smaller than an opening diameter of the concave portion is formed in the concave portion by causing the directed self-assembly material to be directed self-assembled.

Abstract translation: 在根据本实施例的图案形成方法中，在基材上方形成具有第一图案的第一引导层。 形成与第一图案相交的第二图案的第二引导层。 引导自组装材料被引入由第一和第二引导层包围的凹部中。 通过使指向的自组装材料被引导自组装，在凹部中形成具有比凹部的开口直径小的直径的定向自组装图案。