公开(公告)号：US09660071B2

公开(公告)日：2017-05-23

申请号：US15059267

申请日：2016-03-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiroaki Katou ,  Tatsuya Nishiwaki ,  Masatoshi Arai ,  Hiroaki Katsuda ,  Chikako Yoshioka ,  Yoshitaka Hokomoto

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductive layer, a gate electrode, and a first electrode. The conductive layer includes a first portion, a second portion, and a third portion. The first portion is surrounded by the first semiconductor region via a first insulating portion. The second portion extends in a second direction, is provided on the first semiconductor region, and is provided on the second region. The third portion is connected between the first portion and the second portion and extends in a third direction. The first electrode is electrically connected to the third semiconductor region and the conductive layer. The second portion electrically connects the first electrode to the third portion.

公开(公告)号：US20170040252A1

公开(公告)日：2017-02-09

申请号：US15015550

申请日：2016-02-04

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tatsuya Nishiwaki ,  Masatoshi Arai ,  Hiroaki Katou ,  Hiroaki Katsuda ,  Chikako Yoshioka ,  Rieko Matoba

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L29/423

CPC classification number: H01L21/76877 ,  H01L23/528 ,  H01L23/53295 ,  H01L29/4236

Abstract: According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate interconnect, a second insulating layer, and a first electrode. The first semiconductor region includes a first region and a second region provided around the first region. The gate interconnect is provided on the second region. The gate interconnect includes a first portion and a second portion provided around the second portion. A thickness in the first direction of the second portion is thinner than a thickness in the first direction of the first portion. A length in the second direction of the gate interconnect is longer than a length in the third direction of the gate electrode. The first electrode contacts the gate interconnect.

Abstract translation: 根据一个实施例，半导体器件包括第一导电类型的第一半导体区域，第二导电类型的第二半导体区域，第一导电类型的第三半导体区域，栅极电极，栅极互连，第二绝缘体 层和第一电极。 第一半导体区域包括设置在第一区域周围的第一区域和第二区域。 栅极互连设置在第二区域上。 栅极互连包括围绕第二部分设置的第一部分和第二部分。 第二部分的第一方向上的厚度比第一部分的第一方向上的厚度薄。 栅极互连的第二方向上的长度比栅电极的第三方向上的长度长。 第一电极接触栅互连。

公开(公告)号：US09559057B1

公开(公告)日：2017-01-31

申请号：US15015550

申请日：2016-02-04

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tatsuya Nishiwaki ,  Masatoshi Arai ,  Hiroaki Katou ,  Hiroaki Katsuda ,  Chikako Yoshioka ,  Rieko Matoba

IPC: H01L21/44 ,  H01L23/28 ,  H01L23/528 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L23/528 ,  H01L23/53295 ,  H01L29/4236

Abstract: According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate interconnect, a second insulating layer, and a first electrode. The first semiconductor region includes a first region and a second region provided around the first region. The gate interconnect is provided on the second region. The gate interconnect includes a first portion and a second portion provided around the second portion. A thickness in the first direction of the second portion is thinner than a thickness in the first direction of the first portion. A length in the second direction of the gate interconnect is longer than a length in the third direction of the gate electrode. The first electrode contacts the gate interconnect.

Abstract translation: 根据一个实施例，半导体器件包括第一导电类型的第一半导体区域，第二导电类型的第二半导体区域，第一导电类型的第三半导体区域，栅极电极，栅极互连，第二绝缘体 层和第一电极。 第一半导体区域包括设置在第一区域周围的第一区域和第二区域。 栅极互连设置在第二区域上。 栅极互连包括围绕第二部分设置的第一部分和第二部分。 第二部分的第一方向上的厚度比第一部分的第一方向上的厚度薄。 栅极互连的第二方向上的长度比栅电极的第三方向上的长度长。 第一电极接触栅互连。