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公开(公告)号：US20150364562A1
公开(公告)日：2015-12-17
申请号：US14641230
申请日：2015-03-06
IPC分类号： H01L29/47 , H01L29/812 , H01L29/66 , H01L29/423
CPC分类号： H01L29/66734 , H01L29/1095 , H01L29/407 , H01L29/66143 , H01L29/7806 , H01L29/7813 , H01L29/872
摘要： A semiconductor device includes a first semiconductor layer that includes a first region and a second region, a second semiconductor layer that is provided on an upper side of the first semiconductor layer, a third semiconductor layer that is selectively provided on an upper side of the second semiconductor layer, a control electrode provided in the second semiconductor layer and the third semiconductor layer through an insulation film, a first conductor that is provided in the first semiconductor layer so as to be in contact with the control electrode and the first semiconductor layer through the insulation film and is positioned further on a first semiconductor layer side than the control electrode, a second conductor that extends in a direction from the third semiconductor layer to the first semiconductor layer in the second region and is provided in the first semiconductor layer through an insulation film, a first electrode that is electrically connected to the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and a second electrode that is electrically connected to the first semiconductor layer.
摘要翻译： 半导体器件包括：第一半导体层，其包括第一区域和第二区域;第二半导体层，设置在第一半导体层的上侧;第三半导体层，其选择性地设置在第二半导体层的第二区域的上侧; 半导体层，通过绝缘膜设置在第二半导体层中的控制电极和第三半导体层，第一导体，其设置在第一半导体层中，以便通过所述第一半导体层与控制电极和第一半导体层接触 绝缘膜并且位于比所述控制电极的第一半导体层一侧更远的第二导体，所述第二导体在所述第二区域中从所述第三半导体层到所述第一半导体层的方向延伸，并且通过绝缘体设置在所述第一半导体层中 薄膜，电连接到第一半导体的第一电极 层，第二半导体层和第三半导体层，以及电连接到第一半导体层的第二电极。
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公开(公告)号：US09379216B2
公开(公告)日：2016-06-28
申请号：US14160078
申请日：2014-01-21
CPC分类号： H01L29/66719 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： According to an embodiment, a method for manufacturing a semiconductor device includes forming a gate trench extending into a first semiconductor layer; forming a gate insulating film on an internal wall of the gate trench; forming a polysilicon in the gate trench; etching the polysilicon into the gate trench; forming an interlayer insulating film on the polysilicon; etching the first semiconductor layer so as to project the interlayer insulating film from the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; forming a third semiconductor layer on the second semiconductor layer; forming a sidewall contacting a side face of the interlayer insulating film; forming a fourth semiconductor layer of the second conductivity type in the second semiconductor layer; and forming a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer.
摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括形成延伸到第一半导体层中的栅极沟槽; 在栅极沟槽的内壁上形成栅极绝缘膜; 在栅沟中形成多晶硅; 将多晶硅蚀刻到栅极沟槽中; 在多晶硅上形成层间绝缘膜; 蚀刻所述第一半导体层以使所述层间绝缘膜从所述第一半导体层突出; 在所述第一半导体层上形成第二半导体层; 在所述第二半导体层上形成第三半导体层; 形成与所述层间绝缘膜的侧面接触的侧壁; 在第二半导体层中形成第二导电类型的第四半导体层; 以及形成与第三半导体层和第四半导体层电连接的第一电极。
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公开(公告)号：US09917183B2
公开(公告)日：2018-03-13
申请号：US14819068
申请日：2015-08-05
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/78 , H01L29/40 , H01L29/66 , H01L29/417
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/66734
摘要： A semiconductor device is provided including a first electrode and a first semiconductor layer of a first conductivity type connected to the first electrode. The semiconductor device further includes a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a second electrode provided on the third semiconductor layer. The semiconductor device further includes a third electrode disposed between the first electrode and the second electrode. The semiconductor device further includes a fourth electrode having an upper end connected to the second electrode, where the fourth electrode has a higher resistivity than the second electrode.
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公开(公告)号：US09660071B2
公开(公告)日：2017-05-23
申请号：US15059267
申请日：2016-03-02
发明人： Hiroaki Katou , Tatsuya Nishiwaki , Masatoshi Arai , Hiroaki Katsuda , Chikako Yoshioka , Yoshitaka Hokomoto
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42376 , H01L29/4238 , H01L29/66734
摘要： A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductive layer, a gate electrode, and a first electrode. The conductive layer includes a first portion, a second portion, and a third portion. The first portion is surrounded by the first semiconductor region via a first insulating portion. The second portion extends in a second direction, is provided on the first semiconductor region, and is provided on the second region. The third portion is connected between the first portion and the second portion and extends in a third direction. The first electrode is electrically connected to the third semiconductor region and the conductive layer. The second portion electrically connects the first electrode to the third portion.
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公开(公告)号：US20140284708A1
公开(公告)日：2014-09-25
申请号：US14160078
申请日：2014-01-21
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66719 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： According to an embodiment, a method for manufacturing a semiconductor device includes forming a gate trench extending into a first semiconductor layer; forming a gate insulating film on an internal wall of the gate trench; forming a polysilicon in the gate trench; etching the polysilicon into the gate trench; forming an interlayer insulating film on the polysilicon; etching the first semiconductor layer so as to project the interlayer insulating film from the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; forming a third semiconductor layer on the second semiconductor layer; forming a sidewall contacting a side face of the interlayer insulating film; forming a fourth semiconductor layer of the second conductivity type in the second semiconductor layer; and forming a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer.
摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括形成延伸到第一半导体层中的栅极沟槽; 在栅极沟槽的内壁上形成栅极绝缘膜; 在栅沟中形成多晶硅; 将多晶硅蚀刻到栅极沟槽中; 在多晶硅上形成层间绝缘膜; 蚀刻所述第一半导体层以使所述层间绝缘膜从所述第一半导体层突出; 在所述第一半导体层上形成第二半导体层; 在所述第二半导体层上形成第三半导体层; 形成与所述层间绝缘膜的侧面接触的侧壁; 在第二半导体层中形成第二导电类型的第四半导体层; 以及形成与第三半导体层和第四半导体层电连接的第一电极。
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