公开(公告)号：US20130146962A1

公开(公告)日：2013-06-13

申请号：US13598942

申请日：2012-08-30

申请人： Jung Ryul AHN ,  Yun Kyoung Lee

发明人： Jung Ryul AHN ,  Yun Kyoung Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11565 ,  H01L27/11568

摘要： A semiconductor device includes a plurality of first trenches having a first depth formed in a semiconductor substrate, a plurality of second trenches having a second depth formed in the semiconductor substrate, wherein the second depth is different from the first depth and the second trenches are formed between the first trenches, a plurality of isolation layers formed at the plurality of first trenches and the plurality of second trenches, wherein the isolation layers have upper portions formed above the semiconductor substrate, and a plurality of memory cells formed over the semiconductor substrate between the isolation layers.

摘要翻译： 半导体器件包括多个第一沟槽，其具有形成在半导体衬底中的第一深度，多个第二沟槽，其具有形成在半导体衬底中的第二深度，其中第二深度不同于第一深度，并且形成第二沟槽 在所述第一沟槽之间，形成在所述多个第一沟槽和所述多个第二沟槽中的多个隔离层，其中所述隔离层具有形成在所述半导体衬底上方的上部，以及形成在所述半导体衬底之上的多个存储单元 隔离层。

公开(公告)号：US20130049087A1

公开(公告)日：2013-02-28

申请号：US13596704

申请日：2012-08-28

申请人： Jung Ryul AHN ,  Yun Kyoung LEE

发明人： Jung Ryul AHN ,  Yun Kyoung LEE

IPC分类号： H01L29/94 ,  H01L21/762

CPC分类号： H01L27/10844 ,  H01L21/28008 ,  H01L23/5223 ,  H01L27/105 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.

公开(公告)号：US20130146984A1

公开(公告)日：2013-06-13

申请号：US13601437

申请日：2012-08-31

申请人： Jung Ryul AHN

发明人： Jung Ryul AHN

IPC分类号： H01L21/762 ,  H01L29/78

CPC分类号： H01L27/11519 ,  H01L27/11524 ,  H01L29/40114

摘要： A semiconductor device includes isolation layers formed at isolation regions of a semiconductor substrate, silicon patterns formed over the semiconductor substrate between the isolation layers, insulating layers formed between the silicon patterns and the semiconductor substrate, and junctions formed in the semiconductor substrate between the silicon patterns, wherein each of the silicon patterns has a sloped top surface.

摘要翻译： 半导体器件包括形成在半导体衬底的隔离区域处的隔离层，形成在隔离层之间的半导体衬底上的硅图案，形成在硅图案和半导体衬底之间的绝缘层，以及在硅图案之间形成在半导体衬底中的结 ，其中每个硅图案具有倾斜的顶表面。

公开(公告)号：US20120120725A1

公开(公告)日：2012-05-17

申请号：US13297467

申请日：2011-11-16

申请人： Jung Ryul AHN ,  Sang Hyun OH ,  Jum Soo KIM

发明人： Jung Ryul AHN ,  Sang Hyun OH ,  Jum Soo KIM

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/16 ,  H01L27/11524

摘要： A method of operating a semiconductor memory device includes a memory array having memory cell strings including a first and a second memory cell groups having memory cells, a first and a second dummy elements, a drain select transistor and a source select transistor, wherein the first memory cell group and the second memory cell group are arranged between the drain select transistor and the source select transistor; connecting electrically the first memory cell group to the second memory cell group during a program operation or a read operation of the first memory cell group or the second memory cell group; and performing separately an erase operation of the first memory cell group and an erase operation of the second memory cell group, selecting simultaneously one of the first dummy element and the second dummy element during the erase operation of the selected memory cell group.

摘要翻译： 一种操作半导体存储器件的方法包括具有存储单元串的存储器阵列，存储单元串包括具有存储单元的第一和第二存储单元组，第一和第二虚设元件，漏极选择晶体管和源选择晶体管，其中第一 存储单元组和第二存储单元组布置在漏极选择晶体管和源极选择晶体管之间; 在第一存储单元组或第二存储单元组的编程操作或读操作期间将第一存储单元组电连接到第二存储单元组; 以及分别执行第一存储单元组的擦除操作和第二存储单元组的擦除操作，在所选存储单元组的擦除操作期间同时选择第一虚拟元件和第二虚设元件中的一个。

公开(公告)号：US20090053871A1

公开(公告)日：2009-02-26

申请号：US12124024

申请日：2008-05-20

申请人： Jung Ryul AHN

发明人： Jung Ryul AHN

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11573

摘要： A semiconductor memory device and method of fabricating a semiconductor memory device, wherein a tunnel insulating layer, a first charge trap layer and an isolation mask layer are sequentially stacked over a semiconductor substrate in which a cell region and a peri region are defined. The isolation mask layer, the first charge trap layer, the tunnel insulating layer and the semiconductor substrate are etched to thereby form trenches. An isolation layer is formed within each trench. The first charge trap layer is exposed by removing the isolation mask layer formed in the cell region. A second charge trap layer is formed on the exposed first charge trap layer and the isolation layer. A blocking layer and a control gate are formed over the semiconductor substrate in which the second charge trap layer is formed.

摘要翻译： 一种半导体存储器件和半导体存储器件的制造方法，其中隧道绝缘层，第一电荷陷阱层和隔离掩模层依次层叠在其中限定了单元区域和周边区域的半导体衬底上。 蚀刻隔离掩模层，第一电荷阱层，隧道绝缘层和半导体衬底，从而形成沟槽。 在每个沟槽内形成隔离层。 通过去除形成在单元区域中的隔离掩模层来暴露第一电荷陷阱层。 在暴露的第一电荷陷阱层和隔离层上形成第二电荷陷阱层。 在其上形成有第二电荷陷阱层的半导体衬底上形成阻挡层和控制栅极。

公开(公告)号：US20110204430A1

公开(公告)日：2011-08-25

申请号：US13097479

申请日：2011-04-29

申请人： Se Jun KIM ,  Eun Seok CHOI ,  Kyoung Hwan PARK ,  Hyun Seung YOO ,  Myung Shik LEE ,  Young Ok HONG ,  Jung Ryul AHN ,  Yong Top KIM ,  Kyung Pil HWANG ,  Won Sic WOO ,  Jae Young PARK ,  Ki Hong LEE ,  Ki Seon PARK ,  Moon Sig JOO

发明人： Se Jun KIM ,  Eun Seok CHOI ,  Kyoung Hwan PARK ,  Hyun Seung YOO ,  Myung Shik LEE ,  Young Ok HONG ,  Jung Ryul AHN ,  Yong Top KIM ,  Kyung Pil HWANG ,  Won Sic WOO ,  Jae Young PARK ,  Ki Hong LEE ,  Ki Seon PARK ,  Moon Sig JOO

IPC分类号： H01L29/792 ,  B82Y99/00

CPC分类号： H01L29/513 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/792

摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.

摘要翻译： 提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。 制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层 在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

公开(公告)号：US20130148398A1

公开(公告)日：2013-06-13

申请号：US13601301

申请日：2012-08-31

申请人： Yong Mook BAEK ,  Jung Ryul AHN

发明人： Yong Mook BAEK ,  Jung Ryul AHN

IPC分类号： H01L29/78 ,  G11C5/02 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L27/11568

摘要： A three-dimensional (3-D) non-volatile memory device according to an embodiment of the present invention includes a plurality of vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of memory cells stacked alternately along the plurality of vertical channel layers, and an air gap formed in the plurality of interlayer insulating layers disposed between the plurality of memory cells, so that capacitance between word lines is reduced to thus improve a program speed.

摘要翻译： 根据本发明实施例的三维（3-D）非易失性存储器件包括从衬底突出的多个垂直沟道层，多个层间绝缘层和沿着 多个垂直沟道层，以及形成在多个存储单元之间的多个层间绝缘层中形成的气隙，从而减小了字线之间的电容从而提高了程序速度。

公开(公告)号：US20130049086A1

公开(公告)日：2013-02-28

申请号：US13596393

申请日：2012-08-28

申请人： Jung Ryul AHN ,  Jum Soo KIM

发明人： Jung Ryul AHN ,  Jum Soo KIM

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L28/60 ,  H01L21/76224 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11529 ,  H01L28/90

摘要： The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.

公开(公告)号：US20080230830A1

公开(公告)日：2008-09-25

申请号：US12052914

申请日：2008-03-21

申请人： Se Jun KIM ,  Eun Seok CHOI ,  Kyoung Hwan PARK ,  Hyun Seung YOO ,  Myung Shik LEE ,  Young Ok HONG ,  Jung Ryul AHN ,  Yong Top KIM ,  Kyung Pil HWANG ,  Won Sic WOO ,  Jae Young PARK ,  Ki Hong LEE ,  Ki Seon PARK ,  Moon Sig JOO

发明人： Se Jun KIM ,  Eun Seok CHOI ,  Kyoung Hwan PARK ,  Hyun Seung YOO ,  Myung Shik LEE ,  Young Ok HONG ,  Jung Ryul AHN ,  Yong Top KIM ,  Kyung Pil HWANG ,  Won Sic WOO ,  Jae Young PARK ,  Ki Hong LEE ,  Ki Seon PARK ,  Moon Sig JOO

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L21/762

CPC分类号： H01L29/513 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/792

摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.

摘要翻译： 提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。 制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层 在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

公开(公告)号：US20120113725A1

公开(公告)日：2012-05-10

申请号：US13344349

申请日：2012-01-05

申请人： Jung Ryul AHN

发明人： Jung Ryul AHN

IPC分类号： G11C16/10

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based on the first data stored in the first main register, storing a result of the first verification operation in the first main register, performing a second program operation on second memory cells based on the second data stored in the second main register, changing the result of the first verification operation, stored in the first main register, into the first data stored in the first sub-register, performing an additional verification operation on the first memory cells on which the first verification operation has been completed, storing a result of the additional verification operation in the first main register, and performing a second verification operation on the second memory cells.

摘要翻译： 非易失性存储器件和编程器件的方法包括：将第一数据存储在第一主存储器和子寄存器中，并将第二数据存储在第二主寄存器和子寄存器中，基于存储的第一数据对第一存储器单元执行第一程序和验证操作 在第一主寄存器中，将第一验证操作的结果存储在第一主寄存器中，基于存储在第二主寄存器中的第二数据对第二存储器单元执行第二编程操作，改变第一验证操作的结果， 存储在第一主寄存器中的第一存储单元中的第一数据存储在第一子寄存器中，对已经完成了第一验证操作的第一存储单元执行附加验证操作，将附加验证操作的结果存储在第一主寄存器中 主寄存器，并对第二存储单元执行第二验证操作。