公开(公告)号：US08901629B2

公开(公告)日：2014-12-02

申请号：US13596704

申请日：2012-08-28

申请人： Jung Ryul Ahn ,  Yun Kyoung Lee

发明人： Jung Ryul Ahn ,  Yun Kyoung Lee

IPC分类号： H01L29/94 ,  H01L23/522 ,  H01L27/105 ,  H01L49/02

CPC分类号： H01L27/10844 ,  H01L21/28008 ,  H01L23/5223 ,  H01L27/105 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.

摘要翻译： 半导体器件包括被划分为单元区域和沿第一方向限定的外围电路区域的半导体衬底，其中外围电路区域被划分为在基本上正交于第一方向的第二方向上限定的第一区域和第二区域; 栅极线形成在电池区域中的半导体衬底上并且布置在第二方向上; 以及包括在半导体衬底上的下电极，电介质层和上电极的电容器，其中第一和第二区域中的下电极在第一方向上彼此分离并在第一区域中彼此分离，电介质 在第二区域中沿着下电极的表面形成层，并且在电介质层上形成上电极。

公开(公告)号：US20130146962A1

公开(公告)日：2013-06-13

申请号：US13598942

申请日：2012-08-30

申请人： Jung Ryul AHN ,  Yun Kyoung Lee

发明人： Jung Ryul AHN ,  Yun Kyoung Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11565 ,  H01L27/11568

摘要： A semiconductor device includes a plurality of first trenches having a first depth formed in a semiconductor substrate, a plurality of second trenches having a second depth formed in the semiconductor substrate, wherein the second depth is different from the first depth and the second trenches are formed between the first trenches, a plurality of isolation layers formed at the plurality of first trenches and the plurality of second trenches, wherein the isolation layers have upper portions formed above the semiconductor substrate, and a plurality of memory cells formed over the semiconductor substrate between the isolation layers.

摘要翻译： 半导体器件包括多个第一沟槽，其具有形成在半导体衬底中的第一深度，多个第二沟槽，其具有形成在半导体衬底中的第二深度，其中第二深度不同于第一深度，并且形成第二沟槽 在所述第一沟槽之间，形成在所述多个第一沟槽和所述多个第二沟槽中的多个隔离层，其中所述隔离层具有形成在所述半导体衬底上方的上部，以及形成在所述半导体衬底之上的多个存储单元 隔离层。

公开(公告)号：US20110198683A1

公开(公告)日：2011-08-18

申请号：US13028364

申请日：2011-02-16

申请人： Yun Kyoung Lee

发明人： Yun Kyoung Lee

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L29/66833

摘要： Patterns of a nonvolatile memory device include a semiconductor substrate that defines active regions extending in a longitudinal direction, an isolation structure formed between the active regions, a tunnel insulating layer formed on the active regions, a charge trap layer formed on the tunnel insulating layer, a first dielectric layer formed on the charge trap layer and the isolation structure, wherein the first dielectric layers is extended along a lateral direction, a control gate layer formed on the first dielectric layer, wherein the control gate layer is extended along the lateral direction, and a second dielectric layer formed on a sidewall of the control gate layer along the lateral direction and coupled to the first dielectric layer.

摘要翻译： 非易失性存储器件的图案包括限定沿纵向延伸的有源区的半导体衬底，形成在有源区之间的隔离结构，形成在有源区上的隧道绝缘层，形成在隧道绝缘层上的电荷陷阱层， 形成在所述电荷陷阱层和所述隔离结构上的第一电介质层，其中所述第一电介质层沿着横向延伸;形成在所述第一介电层上的控制栅极层，其中所述控制栅极层沿着所述横向方向延伸， 以及第二电介质层，其沿着横向方向形成在所述控制栅极层的侧壁上并且耦合到所述第一介电层。

公开(公告)号：US08318591B2

公开(公告)日：2012-11-27

申请号：US13028364

申请日：2011-02-16

申请人： Yun Kyoung Lee

发明人： Yun Kyoung Lee

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L29/66833

摘要： Patterns of a nonvolatile memory device include a semiconductor substrate that defines active regions extending in a longitudinal direction, an isolation structure formed between the active regions, a tunnel insulating layer formed on the active regions, a charge trap layer formed on the tunnel insulating layer, a first dielectric layer formed on the charge trap layer and the isolation structure, wherein the first dielectric layers is extended along a lateral direction, a control gate layer formed on the first dielectric layer, wherein the control gate layer is extended along the lateral direction, and a second dielectric layer formed on a sidewall of the control gate layer along the lateral direction and coupled to the first dielectric layer.

摘要翻译： 非易失性存储器件的图案包括限定沿纵向延伸的有源区的半导体衬底，形成在有源区之间的隔离结构，形成在有源区上的隧道绝缘层，形成在隧道绝缘层上的电荷陷阱层， 形成在所述电荷陷阱层和所述隔离结构上的第一电介质层，其中所述第一电介质层沿着横向延伸;形成在所述第一介电层上的控制栅极层，其中所述控制栅极层沿着所述横向方向延伸， 以及第二电介质层，其沿着横向方向形成在所述控制栅极层的侧壁上并且耦合到所述第一介电层。