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    Built-in self-test circuit for liquid crystal display source driver
    1.
    发明授权
    Built-in self-test circuit for liquid crystal display source driver 有权
    内置自检电路，用于液晶显示源驱动

    公开(公告)号：US08810268B2

    公开(公告)日：2014-08-19

    申请号：US12764346

    申请日：2010-04-21

    申请人： Jui-Cheng Huang ,  Yung-Chow Peng ,  Ruey-Bin Sheen

    发明人： Jui-Cheng Huang ,  Yung-Chow Peng ,  Ruey-Bin Sheen

    IPC分类号： G01R31/3187

    CPC分类号： G09G3/3685 ,  G09G3/006 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2330/12

    摘要： A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver includes at least one digital-to-analog converter (DAC) and at least one buffer coupled to the respective DAC, wherein the buffer is reconfigurable as a comparator. A first input signal and a second input signal are coupled to the comparator. The first input signal is a predetermined reference voltage level. The second input signal is a test offset voltage in a test range.

    摘要翻译： 用于液晶显示器（LCD）源驱动器的内置自检（BIST）电路包括至少一个数模转换器（DAC）和耦合到相应DAC的至少一个缓冲器，其中缓冲器可重新配置 作为比较。 第一输入信号和第二输入信号耦合到比较器。 第一输入信号是预定的参考电压电平。 第二输入信号是测试范围内的测试偏移电压。

    Semiconductor Mismatch Reduction
    2.
    发明申请
    Semiconductor Mismatch Reduction 有权
    半导体失配减少

    公开(公告)号：US20120235208A1

    公开(公告)日：2012-09-20

    申请号：US13048411

    申请日：2011-03-15

    申请人： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

    发明人： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

    IPC分类号： H01L29/12 ,  H01L21/66

    CPC分类号： H01L27/0207

    摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.

    摘要翻译： 公开了一种用于减小密度失配的系统和方法。 一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。 为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。 另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。 一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

    Semiconductor mismatch reduction
    3.
    发明授权
    Semiconductor mismatch reduction 有权
    半导体失配减少

    公开(公告)号：US09287252B2

    公开(公告)日：2016-03-15

    申请号：US13048411

    申请日：2011-03-15

    申请人： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

    发明人： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

    IPC分类号： H01L29/12 ,  H01L27/02

    CPC分类号： H01L27/0207

    摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.

    摘要翻译： 公开了一种用于减小密度失配的系统和方法。 一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。 为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。 另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。 一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

    MEMS modeling system and method
    4.
    发明授权
    MEMS modeling system and method 有权
    MEMS建模系统及方法

    公开(公告)号：US08762925B2

    公开(公告)日：2014-06-24

    申请号：US13029942

    申请日：2011-02-17

    申请人： Tung-Tsun Chen ,  Yung-Chow Peng ,  Jui-Cheng Huang

    发明人： Tung-Tsun Chen ,  Yung-Chow Peng ,  Jui-Cheng Huang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5022 ,  G06F17/5068 ,  G06F2217/02 ,  G06F2217/06

    摘要： A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices.

    摘要翻译： 公开了一种用于对微机电装置进行建模的系统和方法。 一个实施例包括将微机电设计分离成单独的区域并分别对分开的区域进行建模。 参数化参数或参数方程可用于分开的模型。 单独的模型可以集成到MEMS器件模型中。 可以对MEMS器件模型进行测试和校准，然后可以用于为微机电器件的新设计建模。

    MEMS Modeling System and Method
    5.
    发明申请
    MEMS Modeling System and Method 有权
    MEMS建模系统与方法

    公开(公告)号：US20120215497A1

    公开(公告)日：2012-08-23

    申请号：US13029942

    申请日：2011-02-17

    申请人： Tung-Tsun Chen ,  Yung-Chow Peng ,  Jui-Cheng Huang

    发明人： Tung-Tsun Chen ,  Yung-Chow Peng ,  Jui-Cheng Huang

    IPC分类号： G06F17/50 ,  G06F17/10 ,  G06G7/62

    CPC分类号： G06F17/5081 ,  G06F17/5022 ,  G06F17/5068 ,  G06F2217/02 ,  G06F2217/06

    摘要： A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices.

    摘要翻译： 公开了一种用于对微机电装置进行建模的系统和方法。 一个实施例包括将微机电设计分离成单独的区域并分别对分开的区域进行建模。 参数化参数或参数方程可用于分开的模型。 单独的模型可以集成到MEMS器件模型中。 可以对MEMS器件模型进行测试和校准，然后可以用于为微机电器件的新设计建模。

    Small area high performance cell-based thermal diode
    6.
    发明授权
    Small area high performance cell-based thermal diode 有权
    小面积高性能基于电池的热二极管

    公开(公告)号：US09383264B2

    公开(公告)日：2016-07-05

    申请号：US13428549

    申请日：2012-03-23

    申请人： Yung-Chow Peng ,  Ching-Ho Chang ,  Jui-Cheng Huang

    发明人： Yung-Chow Peng ,  Ching-Ho Chang ,  Jui-Cheng Huang

    IPC分类号： G01K7/00 ,  G01K7/01

    CPC分类号： G01K7/01 ,  Y10T307/76

    摘要： A thermal sensing system includes a circuit having a layout including standard cells arranged in rows and columns. First and second current sources provide first and second currents, respectively. The thermal sensing system includes thermal sensing units, first and second switching modules, and an analog to digital converter (ADC). Each thermal sensing unit is configured to provide a voltage drop dependent on a temperature at that thermal sensing unit. The first switching module is configured to select one of the thermal sensing units. The second switching module includes at least one switch controllable by a control signal. The at least one switch is configured to selectively couple the thermal sensing units, based on the control signal, to one of the first and second current sources, via the first switching module. The ADC is configured to convert an analog voltage, provided by the selected thermal sensing unit, to a digital value.

    摘要翻译： 热感测系统包括具有布置成行和列的标准单元的布局的电路。 第一和第二电流源分别提供第一和第二电流。 热感测系统包括热敏单元，第一和第二开关模块以及模数转换器（ADC）。 每个热敏单元被配置成提供取决于该热感测单元处的温度的电压降。 第一开关模块被配置为选择一个热感测单元。 第二开关模块包括可由控制信号控制的至少一个开关。 所述至少一个开关被配置为经由所述第一开关模块将所述热感测单元基于所述控制信号选择性地耦合到所述第一和第二电流源之一。 ADC配置为将所选热敏单元提供的模拟电压转换为数字值。

    Thermal sensor with second-order temperature curvature correction
    7.
    发明授权
    Thermal sensor with second-order temperature curvature correction 有权
    具有二阶温度曲率校正的热传感器

    公开(公告)号：US09016939B2

    公开(公告)日：2015-04-28

    申请号：US13632498

    申请日：2012-10-01

    申请人： Ching-Ho Chang ,  Jui-Cheng Huang ,  Yung-Chow Peng

    发明人： Ching-Ho Chang ,  Jui-Cheng Huang ,  Yung-Chow Peng

    IPC分类号： G01K7/00 ,  G01K7/01

    CPC分类号： G01K7/01 ,  G01K15/005

    摘要： Some embodiments of the present disclosure relate to a stacked integrated chip structure having a thermal sensor that detects a temperature of one or a plurality of integrated chips. In some embodiments, the stacked integrated chip structure has a main integrated chip and a secondary integrated chip located on an interposer wafer. The main integrated chip has a reference voltage source that generates a bias current. The secondary integrated chip has a second thermal diode that receives the bias current and based thereupon generates a second thermal sensed voltage and a second reference voltage that is proportional to a temperature of the secondary integrated chip. A digital thermal sensor within the main integrated chip determines a temperature of the secondary integrated chip based upon as comparison of the second thermal sensed voltage and the reference voltage.

    摘要翻译： 本公开的一些实施例涉及具有检测一个或多个集成芯片的温度的热传感器的堆叠集成芯片结构。 在一些实施例中，堆叠集成芯片结构具有位于插入器晶片上的主集成芯片和次集成芯片。 主集成芯片具有产生偏置电流的参考电压源。 次级集成芯片具有接收偏置电流的第二热二极管，并且基于此产生第二热感测电压和与次级集成芯片的温度成比例的第二参考电压。 基于与第二热感测电压和参考电压的比较，主集成芯片内的数字热传感器确定二次集成芯片的温度。

    Thermal Sensor with Second-Order Temperature Curvature Correction
    10.
    发明申请
    Thermal Sensor with Second-Order Temperature Curvature Correction 有权
    具有二阶温度曲率校正的热传感器

    公开(公告)号：US20140092939A1

    公开(公告)日：2014-04-03

    申请号：US13632498

    申请日：2012-10-01

    申请人： Ching-Ho Chang ,  Jui-Cheng Huang ,  Yung-Chow Peng

    发明人： Ching-Ho Chang ,  Jui-Cheng Huang ,  Yung-Chow Peng

    IPC分类号： G01K7/01 ,  H01L23/544

    CPC分类号： G01K7/01 ,  G01K15/005

    摘要： Some embodiments of the present disclosure relate to a stacked integrated chip structure having a thermal sensor that detects a temperature of one or a plurality of integrated chips. In some embodiments, the stacked integrated chip structure has a main integrated chip and a secondary integrated chip located on an interposer wafer. The main integrated chip has a reference voltage source that generates a bias current. The secondary integrated chip has a second thermal diode that receives the bias current and based thereupon generates a second thermal sensed voltage and a second reference voltage that is proportional to a temperature of the secondary integrated chip. A digital thermal sensor within the main integrated chip determines a temperature of the secondary integrated chip based upon as comparison of the second thermal sensed voltage and the reference voltage.

    摘要翻译： 本公开的一些实施例涉及具有检测一个或多个集成芯片的温度的热传感器的堆叠集成芯片结构。 在一些实施例中，堆叠集成芯片结构具有位于插入器晶片上的主集成芯片和次集成芯片。 主集成芯片具有产生偏置电流的参考电压源。 次级集成芯片具有接收偏置电流的第二热二极管，并且基于此产生第二热感测电压和与次级集成芯片的温度成比例的第二参考电压。 基于与第二热感测电压和参考电压的比较，主集成芯片内的数字热传感器确定二次集成芯片的温度。