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公开(公告)号：US09383264B2
公开(公告)日：2016-07-05
申请号：US13428549
申请日：2012-03-23
Applicant: Yung-Chow Peng , Ching-Ho Chang , Jui-Cheng Huang
Inventor： Yung-Chow Peng , Ching-Ho Chang , Jui-Cheng Huang
CPC classification number: G01K7/01 , Y10T307/76
Abstract: A thermal sensing system includes a circuit having a layout including standard cells arranged in rows and columns. First and second current sources provide first and second currents, respectively. The thermal sensing system includes thermal sensing units, first and second switching modules, and an analog to digital converter (ADC). Each thermal sensing unit is configured to provide a voltage drop dependent on a temperature at that thermal sensing unit. The first switching module is configured to select one of the thermal sensing units. The second switching module includes at least one switch controllable by a control signal. The at least one switch is configured to selectively couple the thermal sensing units, based on the control signal, to one of the first and second current sources, via the first switching module. The ADC is configured to convert an analog voltage, provided by the selected thermal sensing unit, to a digital value.
Abstract translation: 热感测系统包括具有布置成行和列的标准单元的布局的电路。 第一和第二电流源分别提供第一和第二电流。 热感测系统包括热敏单元，第一和第二开关模块以及模数转换器（ADC）。 每个热敏单元被配置成提供取决于该热感测单元处的温度的电压降。 第一开关模块被配置为选择一个热感测单元。 第二开关模块包括可由控制信号控制的至少一个开关。 所述至少一个开关被配置为经由所述第一开关模块将所述热感测单元基于所述控制信号选择性地耦合到所述第一和第二电流源之一。 ADC配置为将所选热敏单元提供的模拟电压转换为数字值。
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公开(公告)号：US09016939B2
公开(公告)日：2015-04-28
申请号：US13632498
申请日：2012-10-01
Applicant: Ching-Ho Chang , Jui-Cheng Huang , Yung-Chow Peng
Inventor： Ching-Ho Chang , Jui-Cheng Huang , Yung-Chow Peng
CPC classification number: G01K7/01 , G01K15/005
Abstract: Some embodiments of the present disclosure relate to a stacked integrated chip structure having a thermal sensor that detects a temperature of one or a plurality of integrated chips. In some embodiments, the stacked integrated chip structure has a main integrated chip and a secondary integrated chip located on an interposer wafer. The main integrated chip has a reference voltage source that generates a bias current. The secondary integrated chip has a second thermal diode that receives the bias current and based thereupon generates a second thermal sensed voltage and a second reference voltage that is proportional to a temperature of the secondary integrated chip. A digital thermal sensor within the main integrated chip determines a temperature of the secondary integrated chip based upon as comparison of the second thermal sensed voltage and the reference voltage.
Abstract translation: 本公开的一些实施例涉及具有检测一个或多个集成芯片的温度的热传感器的堆叠集成芯片结构。 在一些实施例中，堆叠集成芯片结构具有位于插入器晶片上的主集成芯片和次集成芯片。 主集成芯片具有产生偏置电流的参考电压源。 次级集成芯片具有接收偏置电流的第二热二极管，并且基于此产生第二热感测电压和与次级集成芯片的温度成比例的第二参考电压。 基于与第二热感测电压和参考电压的比较，主集成芯片内的数字热传感器确定二次集成芯片的温度。
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3.发明申请Systems And Methods Providing Active And Passive Charge Sharing In A Digital To Analog Converter 有权在数模转换器中提供主动和被动电荷共享的系统和方法公开(公告)号：US20120218235A1
公开(公告)日：2012-08-30
申请号：US13035444
申请日：2011-02-25
Applicant: Yung-Chow Peng , Jui-Cheng Huang , Ching-Ho Chang , Nang Ping Tu
Inventor： Yung-Chow Peng , Jui-Cheng Huang , Ching-Ho Chang , Nang Ping Tu
CPC classification number: H03M1/68 , G09G3/3688 , G09G2300/023 , G09G2310/027 , G09G2330/023 , H03M1/804
Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.
Abstract translation: 一种用于将多位数字值转换为模拟值的方法。 该方法包括在第一转换周期中，使用无源电荷共享将第一组数字位转换为第一模拟电压。 该方法还包括在第二转换周期中，使用有源电荷共享将第二组数字位转换为添加到第一模拟电压的第二模拟电压。 第一组数字位和第二组数字位是多位数字值的不同位。
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4.发明授权Systems and methods providing active and passive charge sharing in a digital to analog converter 有权在数模转换器中提供有源和无源电荷共享的系统和方法公开(公告)号：US08884797B2
公开(公告)日：2014-11-11
申请号：US13035444
申请日：2011-02-25
Applicant: Yung-Chow Peng , Jui-Cheng Huang , Ching-Ho Chang , Nang Ping Tu
Inventor： Yung-Chow Peng , Jui-Cheng Huang , Ching-Ho Chang , Nang Ping Tu
CPC classification number: H03M1/68 , G09G3/3688 , G09G2300/023 , G09G2310/027 , G09G2330/023 , H03M1/804
Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.
Abstract translation: 一种用于将多位数字值转换为模拟值的方法。 该方法包括在第一转换周期中，使用无源电荷共享将第一组数字位转换为第一模拟电压。 该方法还包括在第二转换周期中，使用有源电荷共享将第二组数字位转换为添加到第一模拟电压的第二模拟电压。 第一组数字位和第二组数字位是多位数字值的不同位。
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公开(公告)号：US20140092939A1
公开(公告)日：2014-04-03
申请号：US13632498
申请日：2012-10-01
Applicant: Ching-Ho Chang , Jui-Cheng Huang , Yung-Chow Peng
Inventor： Ching-Ho Chang , Jui-Cheng Huang , Yung-Chow Peng
IPC: G01K7/01 , H01L23/544
CPC classification number: G01K7/01 , G01K15/005
Abstract: Some embodiments of the present disclosure relate to a stacked integrated chip structure having a thermal sensor that detects a temperature of one or a plurality of integrated chips. In some embodiments, the stacked integrated chip structure has a main integrated chip and a secondary integrated chip located on an interposer wafer. The main integrated chip has a reference voltage source that generates a bias current. The secondary integrated chip has a second thermal diode that receives the bias current and based thereupon generates a second thermal sensed voltage and a second reference voltage that is proportional to a temperature of the secondary integrated chip. A digital thermal sensor within the main integrated chip determines a temperature of the secondary integrated chip based upon as comparison of the second thermal sensed voltage and the reference voltage.
Abstract translation: 本公开的一些实施例涉及具有检测一个或多个集成芯片的温度的热传感器的堆叠集成芯片结构。 在一些实施例中，堆叠集成芯片结构具有位于插入器晶片上的主集成芯片和次集成芯片。 主集成芯片具有产生偏置电流的参考电压源。 次级集成芯片具有接收偏置电流的第二热二极管，并且基于此产生第二热感测电压和与次级集成芯片的温度成比例的第二参考电压。 基于与第二热感测电压和参考电压的比较，主集成芯片内的数字热传感器确定二次集成芯片的温度。
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Patent Agency Ranking
公开(公告)号：US08810268B2
公开(公告)日：2014-08-19
申请号：US12764346
申请日：2010-04-21
Applicant: Jui-Cheng Huang , Yung-Chow Peng , Ruey-Bin Sheen
Inventor： Jui-Cheng Huang , Yung-Chow Peng , Ruey-Bin Sheen
IPC: G01R31/3187
CPC classification number: G09G3/3685 , G09G3/006 , G09G2310/027 , G09G2310/0291 , G09G2330/12
Abstract: A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver includes at least one digital-to-analog converter (DAC) and at least one buffer coupled to the respective DAC, wherein the buffer is reconfigurable as a comparator. A first input signal and a second input signal are coupled to the comparator. The first input signal is a predetermined reference voltage level. The second input signal is a test offset voltage in a test range.
Abstract translation: 用于液晶显示器（LCD）源驱动器的内置自检（BIST）电路包括至少一个数模转换器（DAC）和耦合到相应DAC的至少一个缓冲器，其中缓冲器可重新配置 作为比较。 第一输入信号和第二输入信号耦合到比较器。 第一输入信号是预定的参考电压电平。 第二输入信号是测试范围内的测试偏移电压。
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公开(公告)号：US08762925B2
公开(公告)日：2014-06-24
申请号：US13029942
申请日：2011-02-17
Applicant: Tung-Tsun Chen , Yung-Chow Peng , Jui-Cheng Huang
Inventor： Tung-Tsun Chen , Yung-Chow Peng , Jui-Cheng Huang
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5022 , G06F17/5068 , G06F2217/02 , G06F2217/06
Abstract: A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices.
Abstract translation: 公开了一种用于对微机电装置进行建模的系统和方法。 一个实施例包括将微机电设计分离成单独的区域并分别对分开的区域进行建模。 参数化参数或参数方程可用于分开的模型。 单独的模型可以集成到MEMS器件模型中。 可以对MEMS器件模型进行测试和校准，然后可以用于为微机电器件的新设计建模。
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公开(公告)号：US20120215497A1
公开(公告)日：2012-08-23
申请号：US13029942
申请日：2011-02-17
Applicant: Tung-Tsun Chen , Yung-Chow Peng , Jui-Cheng Huang
Inventor： Tung-Tsun Chen , Yung-Chow Peng , Jui-Cheng Huang
CPC classification number: G06F17/5081 , G06F17/5022 , G06F17/5068 , G06F2217/02 , G06F2217/06
Abstract: A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices.
Abstract translation: 公开了一种用于对微机电装置进行建模的系统和方法。 一个实施例包括将微机电设计分离成单独的区域并分别对分开的区域进行建模。 参数化参数或参数方程可用于分开的模型。 单独的模型可以集成到MEMS器件模型中。 可以对MEMS器件模型进行测试和校准，然后可以用于为微机电器件的新设计建模。
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9.发明授权Buffer operational amplifier with self-offset compensator and embedded segmented DAC for improved linearity LCD driver 有权具有自偏置补偿器和嵌入式分段DAC的缓冲运算放大器，用于改进线性LCD驱动器公开(公告)号：US08476971B2
公开(公告)日：2013-07-02
申请号：US12889492
申请日：2010-09-24
Applicant: Yung-Chow Peng , Wen-Shen Chou , Ching-Ho Chang , Wan-Te Chen
Inventor： Yung-Chow Peng , Wen-Shen Chou , Ching-Ho Chang , Wan-Te Chen
IPC: G06G7/12
CPC classification number: G09G3/3688 , G09G2310/027
Abstract: A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.
Abstract translation: 驱动器利用运算放大器的端子的选择性偏置来减小运算放大器输出中的偏移。 每个运算放大器输入包括包括NMOS晶体管和PMOS晶体管的差分输入对晶体管。 在输入电压范围的低端和高端，这些晶体管选择性地和单独地耦合到标准输入或偏置为导通，以便补偿偏移补偿。 晶体管以常规方式偏置，用于在电压范围的低端和高端之间的输入电压。
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公开(公告)号：US08719755B2
公开(公告)日：2014-05-06
申请号：US13562638
申请日：2012-07-31
Applicant: Wen-Shen Chou , Yung-Chow Peng , Chih-Chiang Chang , Chin-Hua Wen
Inventor： Wen-Shen Chou , Yung-Chow Peng , Chih-Chiang Chang , Chin-Hua Wen
IPC: G06F17/50
CPC classification number: G06F17/5068
Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.
Abstract translation: 除此之外，本文提供了用于分级虚拟插入的一种或多种技术和所得到的阵列。 例如，阵列是金属氧化物半导体（MOS）阵列，金属氧化物金属（MOM）阵列或电阻阵列。 在一些实施例中，基于与第一区域相关联的第一图案密度与与第二区域相关联的第二图案密度之间的密度梯度来识别第一区域和第二区域。 例如，第一图案密度和第二图案密度是门密度和/或多密度。 为此，在第一区域和第二区域之间插入虚拟区域，虚拟区域包括基于第一相邻图案密度和第二相邻图案密度的渐变图案密度。 以这种方式，提供分级虚拟插入，从而提高阵列的边缘单元性能。
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