-
公开(公告)号：US06967508B2
公开(公告)日：2005-11-22
申请号：US10794833
申请日：2004-03-04
CPC classification number: H03K5/00006
Abstract: The frequency doubling circuit and method provides an output signal with stable frequency and a 50% duty cycle. The frequency of the output signal is two times a frequency of the input signal. The circuit only requires four comparators, eight small capacitors, and some switches and transistors for frequency doubling applications. With the help of feedforward structure, the circuit has an almost-instantaneous response. The performance of the provided frequency doubling circuit and method is independent of the frequency and duty cycle of input signal, power supply voltage, temperature, and process variations.
-
公开(公告)号：US20050194999A1
公开(公告)日：2005-09-08
申请号：US10794833
申请日：2004-03-04
CPC classification number: H03K5/00006
Abstract: The frequency doubling circuit and method provides an output signal with stable frequency and a 50% duty cycle. The frequency of the output signal is two times a frequency of the input signal. The circuit only requires four comparators, eight small capacitors, and some switches and transistors for frequency doubling applications. With the help of feedforward structure, the circuit has an almost-instantaneous response. The performance of the provided frequency doubling circuit and method is independent of the frequency and duty cycle of input signal, power supply voltage, temperature, and process variations.
Abstract translation: 倍频电路和方法提供稳定频率和占空比为50％的输出信号。 输出信号的频率是输入信号频率的两倍。 该电路只需要四个比较器，八个小电容器和一些用于倍频应用的开关和晶体管。 在前馈结构的帮助下，电路具有几乎瞬时的响应。 提供的倍频电路和方法的性能与输入信号的频率和占空比，电源电压，温度和工艺变化无关。
-
公开(公告)号：US20240378602A1
公开(公告)日：2024-11-14
申请号：US18783351
申请日：2024-07-24
Applicant: Jun Chen
Inventor： Jun Chen
Abstract: The present disclosure provides a method and system for generating and reading a payment file and a non-transitory computer-readable storage medium, and relates to the technical field of Internet payment. The method includes: generating a payment file tag according to a payment attribute, where the payment attribute includes: an issuer blockchain address and a data file price; reading the data file and determining a data content of the payment file according to the payment attribute; and merging the payment file tag and the data content of the payment file to generate a payment file. By inventing the payment file or embedding the payment attribute into the data file, the present disclosure meets a demand of directly issuing digital files to users by a copyright owner.
-
公开(公告)号：USD1019259S1
公开(公告)日：2024-03-26
申请号：US29911297
申请日：2023-08-31
Applicant: Jun Chen
Designer： Jun Chen
Abstract: FIG. 1 is a top perspective view of a bottle cap, showing my new design;
FIG. 2 is a bottom perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a rear view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top view thereof; and,
FIG. 8 is a bottom view thereof.
The dashed broken lines depict portions of the bottle cap that form no part of the claim design.-
公开(公告)号：US11569440B2
公开(公告)日：2023-01-31
申请号：US15412076
申请日：2017-01-23
Applicant: Yimin Guo , Rongfu Xiao , Jun Chen
Inventor： Yimin Guo , Rongfu Xiao , Jun Chen
Abstract: The invention disclosed a method to make an implanted hard mask with ultra-small dimensions for fabricating integrated nonvolatile random access memory. Instead of directly depositing hard mask material on top of the memory film stack element, we first make ultra-small VIA holes on a pattern transfer molding (PTM) layer using a reverse memory mask, then fill in the hard mask material into the VIA holes within the PTM material. Ultra-small hard mask pillars are formed after removing the PTM material. To improve the adhesion of the hard mask pillars with the underneath memory stack element, a hard mask sustaining element (HMSE) is added below PTM. Due to a better materials adhesion between HMSE and the hard mask, a stronger hard mask array can be formed.
-
Patent Agency Ranking
公开(公告)号：US20210343934A1
公开(公告)日：2021-11-04
申请号：US16865810
申请日：2020-05-04
Applicant: Yimin Guo , Rongfu Xiao , Jun Chen
Inventor： Yimin Guo , Rongfu Xiao , Jun Chen
Abstract: The invention comprises a novel composite multi-stack seed layer (CMSL) having lattice constant matched crystalline structure with the Co layer in above perpendicular magnetic pinning layer (pMPL) so that an excellent epitaxial growth of magnetic super lattice pinning layer [Co/(Pt, Pd or Ni)]n along its FCC (111) orientation can be achieved, resulting in a significant enhancement of perpendicular magnetic anisotropy (PMA) for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.
-
公开(公告)号：US20210327960A1
公开(公告)日：2021-10-21
申请号：US16849571
申请日：2020-04-15
Applicant: RONGFU XIAO , Yimin Guo , Jun Chen
Inventor： RONGFU XIAO , Yimin Guo , Jun Chen
Abstract: An ultra-fast magnetic random access memory (MRAM) comprises a three terminal bottom-pinned composite SOT magnetic tunneling junction (bCSOT-MTJ) element including (counting from top to bottom) a magnetic flux guide (MFG) having a very high magnetic permeability, a spin Hall channel (SHC) having a large positive spin Hall angle, an in-plane magnetic memory (MM) layer, a tunnel barrier (TB) layer, and a magnetic pinning stack (MPS) having a synthetic antiparallel coupling pinned by an antiferromagnetic material. The magnetic writing is significantly boosted by a combined effort of enhanced spin orbit torque (SOT) and Lorentz force generated by current-flowing wire (CFW) in the SHC layer and spin transfer torque (STT) by a current flowing through the MTJ stack, and further enhanced by a magnetic close loop formed at the cross section of MFG/SHC/MM tri-layer. Such bCSOT-MTJ element will have a very fast (down to picoseconds) switching speed and consume much less power suitable level 1 or 2 cache application for SMRAM, CPU, GPU and TPU.
-
公开(公告)号：US11081154B1
公开(公告)日：2021-08-03
申请号：US16773283
申请日：2020-01-27
Applicant: Rongfu Xiao , Yimin Guo , Jun Chen
Inventor： Rongfu Xiao , Yimin Guo , Jun Chen
Abstract: The present invention discloses an enhanced synthetic antiferromagnetic (eSAF) element with a very strong RKKY coupling comprising a magnetic pinning layer having a face-center-cubic (fcc) crystalline structure and a magnetic reference layer having a body-center-cubic (bcc) crystalline structure which are antiferromagnetically coupled by a composite non-magnetic spacer (CnmS) containing a bi-layer of (Ru, Rh or Ir)/Cr or tri-layer of (Ru, Rh, or Ir)/(W, Mo, or V)/Cr. With such eSAF, a strong magnetic pinning element is formed which can be used to make various thin STT-MRAM film stacks with good thermal and magnetic stability while maintaining high TMR value.
-
9.发明授权公开(公告)号：US09750426B2
公开(公告)日：2017-09-05
申请号：US13301300
申请日：2011-11-21
Applicant: Kiaran P McGee , Richard L Ehman , Stephen M Ansell , Yogesh K Mariappan , Jun Chen
Inventor： Kiaran P McGee , Richard L Ehman , Stephen M Ansell , Yogesh K Mariappan , Jun Chen
CPC classification number: A61B5/055 , A61B5/0051
Abstract: A system and method for determining a response of a tumor following a chemotherapy process includes the use of a magnetic resonance elastography (MRE) driver and a magnetic resonance imaging (MRI) system. The method includes controlling the MRE driver and the MRI system to acquire raw MRE data from the tumor, inverting the raw MRE data to produce an elastogram of the tumor, and determining a response of the tumor to the chemotherapy process from the elastogram.
-
公开(公告)号：US09262035B1
公开(公告)日：2016-02-16
申请号：US13443200
申请日：2012-04-10
Applicant: Paul Gustafson , Hob Anthony Spillane , Jun Chen , Khurram Mahmood
Inventor： Paul Gustafson , Hob Anthony Spillane , Jun Chen , Khurram Mahmood
CPC classification number: G06F3/048 , G06F9/44 , G06F9/451 , G06F17/30572 , G06Q30/02
Abstract: A system for displaying an embedded intelligence applet comprises a processor and a memory. The processor is configured to provide display information to display in the embedded intelligence applet window and to provide an indication to display the embedded intelligence applet window in an opaque mode. The processor is configured to determine whether an indication to activate a window other than the embedded intelligence applet window is received. The processor is configured to provide an indication to display the embedded intelligence applet window in a partially transparent mode in the event that an indication to activate a window other than the embedded intelligence applet window is received. The memory is coupled to the processor and is configured to provide the processor with instructions.
Abstract translation: 用于显示嵌入式智能小应用程序的系统包括处理器和存储器。 处理器被配置为提供显示信息以在嵌入式智能小应用程序窗口中显示并且提供以不透明模式显示嵌入式智能小应用程序窗口的指示。 处理器被配置为确定是否接收到激活除嵌入式智能小程序窗口之外的窗口的指示。 处理器被配置为在接收到激活不同于嵌入式智能小应用程序窗口的窗口的指示的情况下，提供在部分透明模式下显示嵌入式智能小应用程序窗口的指示。 存储器耦合到处理器并且被配置为向处理器提供指令。
-
-
-
-
-
-
-
-
-
Search Results
276
records
(took 0.039 seconds)
