Abstract:
An integrated circuit has a doped silicon semiconductor with regions of insulators and bare silicon. The bare silicon regions are isolated from other bare silicon regions. A semiconductor device on the doped silicon semiconductor has at least two electrical connections to form regions of patterned metal. A metal is electroplated directly on each of the regions of patterned metal to form plated connections without a seed layer. A self-aligned silicide is located under each plated connection, formed by annealing, for the regions of plated metal on bare silicon.
Abstract:
A method for making a master disk to be used in the nanoimprinting process to make patterned-media disks uses an electrically conductive substrate and guided self-assembly of a block copolymer to form patterns of generally radial lines and/or generally concentric rings of one of the block copolymer components. A metal is electroplated onto the substrate in the regions not protected by the lines and/or rings. After removal of the block copolymer component, the remaining metal pattern is used as an etch mask to fabricate either the final master disk or two separate molds that are then used to fabricate the master disk.
Abstract:
A method for self aligning a lapping guide with a structure of a write pole. A write pole is formed over a substrate and an electrically conductive material lapping guide material is deposited in a location that is removed from the write pole. A mask is then formed over a portion of the write pole and a portion of the electrically conductive material. A material removal process such as reactive ion etching can then be performed to remove a portion of the magnetic material that is not protected by the mask structure. An magnetic material is then electroplated over the write pole with the write pole, with the mask still in place. In this way, the electroplated material has an edge that is self aligned with an edge of the electrically conductive lapping guide material, both being defined by the same mask structure.
Abstract:
A patterned perpendicular magnetic recording medium of the type that has spaced-apart pillars with magnetic material on their ends and with nonmagnetic trenches between the pillars is made with a method that allows use of a pre-etched substrate. The substrate has a generally planar surface at the trenches and comprises material that when heated will diffuse into the magnetic recording layer material and chemically react with one or more of the elements typically used in the recording layer. The pillars are formed of material that will not diffuse into the recording layer. After the recording layer is formed over the entire substrate so as to cover both the pillar ends and the trenches, the substrate is annealed. This results in the destruction or at least substantial reduction of any ferromagnetism in the recording layer material in the trenches so that the trenches are nonmagnetic. The annealing does not affect the recording layer on the ends of the pillars because the pillars are formed of material that will not diffuse into the recording layer.
Abstract:
In one illustrative example, a three terminal magnetic sensor (TTM) suitable for use in a magnetic head has a sensor stack structure which includes a base region, a collector region, and an emitter region. A first barrier layer separates the emitter region from the base region, and a second barrier layer separates the collector region from the base region. A plurality of terminals of the TTM include a base lead coupled to the base region, a collector lead coupled to the collector region, and an emitter lead coupled to the emitter region. Preferably, the base region consists of a free layer structure so as to have a relatively small thickness. A pinned layer structure is made part of the emitter region. An in-stack longitudinal biasing layer (LBL) structure is formed in stack with the sensor stack structure and has a magnetic moment that is parallel to a sensing plane of the TTM for magnetically biasing the free layer structure. The in-stack LBL structure is made part of the collector region which also includes a layer of semiconductor material. In one variation, the emitter region has the in-stack LBL structure and the collector region has the pinned layer structure. The TTM may comprise a spin valve transistor (SVT), a magnetic tunnel transistor (MTT), or a double junction structure.
Abstract:
Methods and structures for improving fly height control for thin film write heads utilized in thermally assisted recording are disclosed. Methods include the use of the TAR near field light source to provide a preheating pulse to improve the transient response when moving from one fly height to another prior to writing data. Methods and structures having an additional auxiliary optical heating source to avoid media overheating and replacement of embedded resistive heaters are also disclosed.
Abstract:
A system according to one embodiment comprises a slider having an air bearing surface side and a flex side, the flex side being positioned on an opposite side of the slider as the air bearing surface side; electrical pads on the flex side of the slider; and a heating device in electrical communication with the electrical pads, where the heating device comprises a least one optical element A method according to one embodiment comprises positioning pads of a heating device towards pads on a slider; detecting an impedance in a circuit including the pads of the heating device; moving the heating device relative to the slider to minimize the impedance; and coupling the heating device to the slider. Additional systems and methods are provided.
Abstract:
A method of reducing flux leakage between a main pole and a wrap around shield (WAS) is provided. A gap underneath a main pole is etched. Magnetic material is deposited in the gap. A layer of nonmagnetic material is deposited on the magnetic material, wherein the layer of nonmagnetic material reduces flux leakage between the main pole and the WAS.
Abstract:
Methods and structures for the electroplating on ultra-thin seed layers are disclosed. A dual layer structure is utilized, consisting of a thicker, highly conductive layer surrounding device structures. Within the device die, an ultra-thin seed layer is employed, which is electrically coupled to the conduction layer. Using this technique, electroplating of critical device structures can be carefully controlled and made uniform across the full diameter of the wafer. The technique also allow for the deployment of ultra-thin seed layers of varying thickness and composition in different locations within the circuit device, or in different die on the wafer.
Abstract:
Methods for fabricating a device component are provided. A substrate comprising a RIE stop layer, an oxide layer formed on the RIE stop layer, and a RIE-able layer formed on the oxide layer may be provided. A resist layer may be patterned on the RIE-able layer. A metal layer may be formed on portions of the RIE-able layer that are not covered by the resist layer. The resist layer may be removed and an RIE performed to remove exposed portions of the RIE-able layer and portions of the oxide layer beneath the exposed portions of the RIE-able layer. Thereafter, the metal layer may be removed, and the component may be formed in an opening in the oxide layer formed during the RIE.