公开(公告)号：US20050125623A1

公开(公告)日：2005-06-09

申请号：US10730953

申请日：2003-12-09

申请人： Jason Dale ,  Jonathan DeMent ,  Kimberly Fernsler

发明人： Jason Dale ,  Jonathan DeMent ,  Kimberly Fernsler

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/652

摘要： A method and apparatus for efficiently storing an effective address (EA) in an effective to real address translation (ERAT) table supporting multiple page sizes by adding PSI fields, based on the number of unique page sizes supported, to each ERAT entry and using one ERAT entry to store an EA for a memory page, regardless of page size, by setting the PSI fields to indicate the page size.

摘要翻译： 一种方法和装置，用于通过基于所支持的唯一页面大小的数目添加PSI字段来有效地将有效地址（EA）存储在支持多个页面大小的有效到真实地址转换（ERAT）表中，并且使用一个 ERAT条目通过设置PSI字段来指示页面大小，无论页面大小如何，都可以存储内存页面的EA。

公开(公告)号：US20050182912A1

公开(公告)日：2005-08-18

申请号：US10777906

申请日：2004-02-12

申请人： Jonathan DeMent ,  Kimberly Fernsler ,  Cathy May

发明人： Jonathan DeMent ,  Kimberly Fernsler ,  Cathy May

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/109

摘要： The present invention provides a method and apparatus for efficiently translating an effective address (EA) to a real address (RA) in an Effective to Real Address Translation (ERAT) table, in a main processing unit (MPU) having two or more threads. A thread, using an EA, presents the EA for lookup in the ERAT table. The EA is compared to each entry in the ERAT table. If (i) the EA matches an entry in the ERAT table, (ii) a valid indicator in the matching entry indicates it is valid for other threads but not valid for the thread presenting the EA for lookup, and (iii) the information in the matching entry is correct for the EA presented for lookup, then the valid indicator is set to show that the matching entry is valid for the thread presenting the EA for lookup, in addition to the other threads.

摘要翻译： 本发明提供了一种在具有两个或多个线程的主处理单元（MPU）中有效地将有效地址（EA）转换为有效到实地址转换（ERAT）表中的实际地址（RA）的方法和装置。 使用EA的线程在ERAT表中显示EA进行查找。 将EA与ERAT表中的每个条目进行比较。 如果（i）EA匹配ERAT表中的条目，（ii）匹配条目中的有效指示符表示其对于其他线程有效，但对于呈现EA进行查找的线程无效，以及（iii） 匹配条目对于为查找提供的EA是正确的，则除了其他线程之外，有效指示符被设置为显示匹配条目对于呈现EA进行查找的线程是有效的。

公开(公告)号：US20070288762A1

公开(公告)日：2007-12-13

申请号：US11423312

申请日：2006-06-09

申请人： Jason Dale ,  Jonathan DeMent ,  Clark O'Niell ,  Steven Roberts

发明人： Jason Dale ,  Jonathan DeMent ,  Clark O'Niell ,  Steven Roberts

IPC分类号： G06F12/14

CPC分类号： G06F9/4406 ,  G06F21/575 ,  G06F21/75 ,  G06F21/755 ,  H04L9/08 ,  H04L2209/04 ,  H04L2209/08

摘要： A system and method for masking a boot sequence by providing a dummy processor are provided. With the system and method, one of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. The execution of the masking code on the non-boot processors preferably generates electromagnetic and/or thermal signatures that approximate the signatures of the actual boot code execution on the boot processor. One of the non-boot processors is selected to execute masking code that is different from the other masking code sequence to thereby generate a electromagnetic and/or thermal signature that appears to be unique from an external monitoring perspective.

摘要翻译： 提供了一种通过提供虚拟处理器来掩蔽引导序列的系统和方法。 使用系统和方法，多处理器系统的处理器之一被选择为引导处理器。 多处理器系统的其他处理器执行掩蔽代码，其产生屏蔽实际引导处理器的电磁和/或热特征的电磁和/或热特征。 非启动处理器上的屏蔽码的执行优选地产生近似发动机处理器上的实际启动代码执行的签名的电磁和/或热签名。 选择非引导处理器之一来执行不同于其它掩码代码序列的掩码，从而从外部监视的角度生成似乎是唯一的电磁和/或热签名。

公开(公告)号：US20070198812A1

公开(公告)日：2007-08-23

申请号：US11236835

申请日：2005-09-27

申请人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

发明人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857

摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a main array of storage cells and an auxiliary array of storage cells coupled thereto. When a particular row of the main array includes an instruction that is not ready-to-issue, a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row of the main array may bypass the row including the stalled or not-ready-to-issue instruction. To effect this bypass, the issue queue moves the ready-to-issue instruction to an issue row of the auxiliary array for issuance to an appropriate execution unit. Out-of-order issuance of instructions to the execution units thus continues despite the stalled instruction.

摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括存储单元的主阵列和与其耦合的存储单元的辅助阵列。 当主阵列的特定行包含不能准备发出的指令时，该指令将发生停顿状态。 然而，为了防止整个问题队列和处理器停止，主阵列的另一行中的就绪指令可以绕过包括已停止或尚未准备就绪的指令的行。 为了实现此旁路，问题队列将准备就绪指令移动到辅助阵列的问题行以发布到适当的执行单元。 因此，执行单元的指令的乱序发布仍然停止。

公开(公告)号：US20070118726A1

公开(公告)日：2007-05-24

申请号：US11284681

申请日：2005-11-22

申请人： Christopher Abernathy ,  Jonathan DeMent ,  David Shippy ,  Albert Nordstrand

发明人： Christopher Abernathy ,  Jonathan DeMent ,  David Shippy ,  Albert Nordstrand

IPC分类号： G06F9/44 ,  G06F13/28

CPC分类号： G06F9/30181 ,  G06F9/30076 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3867

摘要： A system and method for dynamic switching between performance schemes is presented. The software program uses an instruction to indicate whether a pacing performance scheme or a flushing performance scheme is to be used. The selection by the software program is stored in a hardware register that the processor uses to determine whether the pacing or flushing performance scheme is used. After setting the performance scheme, subsequent instructions of the software program will be executed using the selected performance scheme. The pacing performance scheme preemptively stalls an instruction that might overload the queue that stores instructions for the Load/Store Unit (LSU). The flushing performance scheme flushes instructions when the LSU storage queue is overloaded and holds the thread that caused the overflow dormant until the queue is no longer full.

摘要翻译： 介绍了性能方案之间动态切换的系统和方法。 软件程序使用指令来指示是否使用起搏性能方案或冲洗性能方案。 软件程序的选择存储在硬件寄存器中，处理器用来确定是否使用起搏或冲洗性能方案。 在设置性能方案之后，将使用所选择的性能方案来执行软件程序的后续指令。 起搏性能方案会先预先停止可能使存储针对加载/存储单元（LSU）的指令的队列过载的指令。 当LSU存储队列过载时，刷新性能方案会刷新指令，并保持导致溢出休眠的线程，直到队列不再满。

公开(公告)号：US20070043931A1

公开(公告)日：2007-02-22

申请号：US11204414

申请日：2005-08-16

申请人： Jonathan DeMent ,  Kurt Feiste ,  Robert Philhower ,  David Shippy

发明人： Jonathan DeMent ,  Kurt Feiste ,  Robert Philhower ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3875

摘要： A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.

摘要翻译： 提出了一种用于高频失速设计的系统和方法。 发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。 在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令 基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。 在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

公开(公告)号：US20060036814A1

公开(公告)日：2006-02-16

申请号：US10916969

申请日：2004-08-12

申请人： Jonathan DeMent ,  Kerey Tassin ,  Thuong Truong

发明人： Jonathan DeMent ,  Kerey Tassin ,  Thuong Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/0837 ,  G06F12/0831

摘要： A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory.

摘要翻译： 创建直写缓存方案。 存储数据命令从处理单元发送到高速缓存阵列的高速缓存行。 然后确定存储数据的地址是否有效，其中来自存储地址的原始数据已经被预先加载到高速缓存中。 根据存储数据的地址是否有效，将一个直写命令发送到系统总线。 总线控制器用于检测直写命令。 如果感测到直写命令，则总线控制器产生清洁命令。 如果检测到直写命令，则将存储数据写入高速缓存阵列，并将数据标记为修改。 如果感测到直写命令，则清除命令由总线控制器发送到系统总线上，从而将修改的数据写入存储器。

公开(公告)号：US20070074005A1

公开(公告)日：2007-03-29

申请号：US11236838

申请日：2005-09-27

申请人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

发明人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3855

摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.

摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括以行和列配置的存储单元矩阵，包括耦合到执行单元的第一行。 显示从空行到无存储单元格时，逐行发行的说明。 当指示向第一行发出时，出现未占用的单元格。 当特定行包含一个尚未准备就绪的指令时，该指令发生停顿状态。 然而，为了防止整个问题队列和处理器停止，另一行中的就绪指令可能绕过包括已停止或尚未就绪的指令的行。 因此，对执行单元的指令的无序发布继续进行。

公开(公告)号：US20050160229A1

公开(公告)日：2005-07-21

申请号：US10759941

申请日：2004-01-16

申请人： Charles Johns ,  Michael Day ,  Jonathan DeMent

发明人： Charles Johns ,  Michael Day ,  Jonathan DeMent

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/654 ,  G06F2212/684

摘要： A method and an apparatus are provided for efficiently managing the operation of a translation buffer. A software and hardware apparatus and method are utilized to pre-load a translation buffer to prevent poor operation as a result of slow warming of a cache.

摘要翻译： 提供了一种用于有效地管理翻译缓冲器的操作的方法和装置。 使用软件和硬件装置和方法来预加载翻译缓冲器，以防止由于缓存缓慢升温而造成的不良操作。

公开(公告)号：US20070113044A1

公开(公告)日：2007-05-17

申请号：US11621315

申请日：2007-01-09

申请人： Michael Day ,  Jonathan DeMent ,  Charles Johns

发明人： Michael Day ,  Jonathan DeMent ,  Charles Johns

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/654 ,  G06F2212/684

摘要： A method and an apparatus are provided for efficiently managing the operation of a translation buffer. A software and hardware apparatus and method are utilized to pre-load a translation buffer to prevent poor operation as a result of slow warming of a cache. A software pre-load mechanism may be provided for preloading a translation lookaside buffer (TLB) via a hardware implemented controller. Following preloading of the TLB, control of accessing the TLB may be handed over to the hardware implemented controller. Upon an application context switch operation, the software preload mechanism may be utilized again to preload the TLB with new translation information for the newly active application instance.

摘要翻译： 提供了一种用于有效地管理翻译缓冲器的操作的方法和装置。 使用软件和硬件装置和方法来预加载翻译缓冲器，以防止由于缓存缓慢升温而造成的不良操作。 可以提供软件预加载机制，用于经由硬件实现的控制器来预加载翻译后备缓冲器（TLB）。 在TLB的预加载之后，可以将访问TLB的控制权交给硬件实现的控制器。 在应用程序上下文切换操作时，可以再次利用软件预载机制来为新活动的应用实例的新的翻译信息预加载TLB。