公开(公告)号：US07968981B2

公开(公告)日：2011-06-28

申请号：US12101915

申请日：2008-04-11

Applicant: Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang ,  YoungChul Kim

Inventor： Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang ,  YoungChul Kim

IPC: H01L23/495

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/49565 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system including: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.

Abstract translation: 一种集成电路封装系统，包括：提供具有安装在其上的集成电路的引线框架; 用封装封装集成电路; 在引线框下方安装蚀刻阻挡层; 并蚀刻引线框架。

公开(公告)号：US20090258494A1

公开(公告)日：2009-10-15

申请号：US12101915

申请日：2008-04-11

Applicant: Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang ,  YoungChul Kim

Inventor： Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang ,  YoungChul Kim

IPC: H01L21/311

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/49565 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system including: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.

Abstract translation: 一种集成电路封装系统，包括：提供具有安装在其上的集成电路的引线框架; 用封装封装集成电路; 在引线框下方安装蚀刻阻挡层; 并蚀刻引线框架。

公开(公告)号：US20110244635A1

公开(公告)日：2011-10-06

申请号：US13159095

申请日：2011-06-13

Applicant: Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang ,  YoungChul Kim

Inventor： Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang ,  YoungChul Kim

IPC: H01L21/56

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/49565 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for manufacture of an integrated circuit package system includes: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.

Abstract translation: 一种用于制造集成电路封装系统的方法，包括：提供具有安装在其上的集成电路的引线框架; 用封装封装集成电路; 在引线框下方安装蚀刻阻挡层; 并蚀刻引线框架。

公开(公告)号：US08501540B2

公开(公告)日：2013-08-06

申请号：US13159095

申请日：2011-06-13

Applicant: Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang ,  YoungChul Kim

Inventor： Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang ,  YoungChul Kim

IPC: H01L21/00

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/49565 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for manufacture of an integrated circuit package system includes: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.

Abstract translation: 一种用于制造集成电路封装系统的方法，包括：提供具有安装在其上的集成电路的引线框架; 用封装封装集成电路; 在引线框下方安装蚀刻阻挡层; 并蚀刻引线框架。

公开(公告)号：US08810019B2

公开(公告)日：2014-08-19

申请号：US13366560

申请日：2012-02-06

Applicant: Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang

Inventor： Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang

IPC: H01L23/02

CPC classification number: H01L23/49575 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system includes a trace frame includes: an encapsulant; a first series of bonding pads along a length of the encapsulant; a second series of the bonding pads along a width of the encapsulant; conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and a first integrated circuit die on the encapsulant and on the conductive traces that extend beyond the first integrated circuit die.

Abstract translation: 集成电路封装系统包括跟踪框架，包括：密封剂; 沿着所述密封剂的长度的第一系列接合焊盘; 沿密封剂的宽度的第二系列接合焊盘; 用于将第一系列的焊盘与一对一对应的第二系列的焊盘连接的导电迹线; 以及第一集成电路管芯在密封剂和导电迹线上延伸超过第一集成电路管芯。

公开(公告)号：US20120133038A1

公开(公告)日：2012-05-31

申请号：US13366560

申请日：2012-02-06

Applicant: Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang

Inventor： Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system includes a trace frame includes: an encapsulant; a first series of bonding pads along a length of the encapsulant; a second series of the bonding pads along a width of the encapsulant; conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and a first integrated circuit die on the encapsulant and on the conductive traces that extend beyond the first integrated circuit die.

Abstract translation: 集成电路封装系统包括跟踪框架，包括：密封剂; 沿着所述密封剂的长度的第一系列接合焊盘; 沿密封剂的宽度的第二系列接合焊盘; 用于将第一系列的焊盘与一对一对应的第二系列的焊盘连接的导电迹线; 以及第一集成电路管芯在密封剂和导电迹线上延伸超过第一集成电路管芯。

公开(公告)号：US08138591B2

公开(公告)日：2012-03-20

申请号：US11860460

申请日：2007-09-24

Applicant: Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang

Inventor： Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang

IPC: H01L23/06

CPC classification number: H01L23/49575 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system comprising forming a trace frame including: fabricating a sacrificial substrate; forming a first series of bonding pads along a length of the sacrificial substrate; forming a second series of the bonding pads along a width of the sacrificial substrate; forming conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and removing the sacrificial substrate.

Abstract translation: 一种集成电路封装系统，包括形成迹线框架，包括：制造牺牲衬底; 沿着所述牺牲衬底的长度形成第一系列接合焊盘; 沿所述牺牲衬底的宽度形成第二系列焊盘; 形成用于将第一系列的接合焊盘一一对应地连接到第二系列的接合焊盘的导电迹线; 并去除牺牲衬底。

公开(公告)号：US20080073770A1

公开(公告)日：2008-03-27

申请号：US11860460

申请日：2007-09-24

Applicant: Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang

Inventor： Jae Hak Yee ,  Junwoo Myung ,  Byoung Wook Jang

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system comprising forming a trace frame including: fabricating a sacrificial substrate; forming a first series of bonding pads along a length of the sacrificial substrate; forming a second series of the bonding pads along a width of the sacrificial substrate; forming conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and removing the sacrificial substrate.

Abstract translation: 一种集成电路封装系统，包括形成迹线框架，包括：制造牺牲衬底; 沿着所述牺牲衬底的长度形成第一系列接合焊盘; 沿所述牺牲衬底的宽度形成第二系列焊盘; 形成用于将第一系列的接合焊盘一一对应地连接到第二系列的接合焊盘的导电迹线; 并去除牺牲衬底。

公开(公告)号：US20080171405A1

公开(公告)日：2008-07-17

申请号：US12014578

申请日：2008-01-15

Applicant: Jae Hak Yee ,  Byoung Wook Jang

Inventor： Jae Hak Yee ,  Byoung Wook Jang

IPC: H01L21/60 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L31/0203 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit package system includes forming an integrated circuit stack having a bottom non-active side and a top non-active side; connecting an internal interconnect between a lead, having a top side and a bottom side, and the integrated circuit stack; and forming an encapsulation, having both a non-elevated portion and an elevated portion, around the integrated circuit stack and the internal interconnect with the top side exposed at the non-elevated portion, and with the bottom side, the bottom non-active side, and the top non-active side exposed.

Abstract translation: 集成电路封装系统包括形成具有底部非有源侧和顶部非有源侧的集成电路堆叠; 连接具有顶侧和底侧的引线与集成电路堆叠之间的内部互连; 并且在集成电路堆叠周围形成具有非升高部分和升高部分的封装以及在非升高部分处暴露的顶侧的内部互连，并且在底侧，底部非活动侧 ，并且顶部的非活动侧暴露。

公开(公告)号：US08847413B2

公开(公告)日：2014-09-30

申请号：US12014578

申请日：2008-01-15

Applicant: Jae Hak Yee ,  Byoung Wook Jang

Inventor： Jae Hak Yee ,  Byoung Wook Jang

IPC: H01L31/0203 ,  H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L25/03 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L31/0203 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit package system includes forming an integrated circuit stack having a bottom non-active side and a top non-active side; connecting an internal interconnect between a lead, having a top side and a bottom side, and the integrated circuit stack; and forming an encapsulation, having both a non-elevated portion and an elevated portion, around the integrated circuit stack and the internal interconnect with the top side exposed at the non-elevated portion, and with the bottom side, the bottom non-active side, and the top non-active side exposed.

Abstract translation: 集成电路封装系统包括形成具有底部非有源侧和顶部非有源侧的集成电路堆叠; 连接具有顶侧和底侧的引线与所述集成电路堆叠之间的内部互连; 并且在集成电路堆叠周围形成具有非升高部分和升高部分的封装以及在非升高部分处暴露的顶侧的内部互连，并且在底侧，底部非活动侧 ，并且顶部的非活动侧暴露。