Invention Grant
- Patent Title: Integrated circuit package system with stacked die
- Patent Title (中): 集成电路封装系统与堆叠裸片
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Application No.: US11860460Application Date: 2007-09-24
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Publication No.: US08138591B2Publication Date: 2012-03-20
- Inventor: Jae Hak Yee , Junwoo Myung , Byoung Wook Jang
- Applicant: Jae Hak Yee , Junwoo Myung , Byoung Wook Jang
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd
- Current Assignee: STATS ChipPAC Ltd
- Current Assignee Address: SG Singapore
- Agent Mikio Ishimaru
- Main IPC: H01L23/06
- IPC: H01L23/06

Abstract:
An integrated circuit package system comprising forming a trace frame including: fabricating a sacrificial substrate; forming a first series of bonding pads along a length of the sacrificial substrate; forming a second series of the bonding pads along a width of the sacrificial substrate; forming conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and removing the sacrificial substrate.
Public/Granted literature
- US20080073770A1 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE Public/Granted day:2008-03-27
Information query
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