知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.013 seconds)

    Methods and apparatus for clock gating processing modules based on hierarchy and workload
    1.
    发明授权
    Methods and apparatus for clock gating processing modules based on hierarchy and workload 有权

    公开(公告)号：US10571988B1

    公开(公告)日：2020-02-25

    申请号：US15866664

    申请日：2018-01-10

    Applicant: Juniper Networks, Inc.

    Inventor： Vaishali Kulkarni ,  Jeffrey G. Libby ,  David J. Ofelt

    IPC: G06F1/00 ,  G06F1/32

    Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to a first processing module and a second processing module. The first processing module has a priority higher than a priority of the second processing module. The dispatch module includes a workload counter associated with the first processing module to provide an indication of a workload at the first processing module. The dispatch module initiates a clock signal at the second processing module only if the indication of the workload at the first processing module satisfies a criterion. The dispatch module sends a data unit to the second processing module for processing only if the indication of the workload at the first processing module satisfies a criterion.

    Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules
    2.
    发明授权
    Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules 有权
    用于限制多个当前变化的方法和装置，同时时钟选通以管理处理器模块的功耗

    公开(公告)号：US09477257B1

    公开(公告)日：2016-10-25

    申请号：US13799210

    申请日：2013-03-13

    Applicant: Juniper Networks, Inc.

    Inventor： Vaishali Kulkarni ,  Jeffrey G. Libby ,  Mihir Wagh

    IPC: G06F1/00 ,  G06F1/08 ,  G06F1/26 ,  G06F1/04 ,  G06F1/32 ,  G06F3/06

    CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/26 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0634 ,  G06F9/4881 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/171

    Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to multiple processing modules, each having a first clock configuration and a second clock configuration. The dispatch module, at a first time, changes a first processing module included in the multiple processing modules from a first clock configuration to a second clock configuration. The dispatch module prohibits, at a second time within a predetermined time period and after the first time, a second processing module included in the multiple processing modules from changing from the first clock configuration to the second clock configuration if an indicator associated with a number of changes of the multiple processing modules between a first clock configuration and a second clock configuration within the predetermined time period and prior to the second time satisfies a criterion.

    Abstract translation: 在存储器或处理设备中的至少一个中实现的调度模块可操作地耦合到多个处理模块，每个处理模块具有第一时钟配置和第二时钟配置。 调度模块首次将包括在多个处理模块中的第一处理模块从第一时钟配置改变为第二时钟配置。 调度模块在预定时间段内和第一次之后的第二时间禁止包括在多个处理模块中的第二处理模块从第一时钟配置改变为第二时钟配置，如果与多个处理模块相关联的指示符 在第一时钟配置和第二时钟配置之间的多个处理模块在预定时间段内和第二时间之间的改变满足标准。

    Use of cache to reduce memory bandwidth pressure with processing pipeline
    3.
    发明授权
    Use of cache to reduce memory bandwidth pressure with processing pipeline 有权
    使用缓存来减少内存带宽压力与处理流水线

    公开(公告)号：US09116814B1

    公开(公告)日：2015-08-25

    申请号：US14092072

    申请日：2013-11-27

    Applicant: JUNIPER NETWORKS, INC.

    Inventor： Jianhui Huang ,  Sharada Yeluri ,  Jean-Marc Frailong ,  Jeffrey G. Libby ,  Anurag P. Gupta ,  Paul Coelho

    IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/0855 ,  G06F12/0815 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/12 ,  Y02D10/13

    Abstract: A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.

    Abstract translation: 数据读/写系统包括系统时钟，单端口存储器，与单端口存储器分开的高速缓存存储器，以及耦合到指令流水线的控制器。 控制器经由指令流水线接收第一数据以写入单端口存储器的地址，并且经由指令流水线接收从单端口存储器读取第二数据的请求。 控制器将第一数据存储在高速缓冲存储器中，并且在系统时钟的一个或多个第一时钟周期期间从高速缓冲存储器或单端口存储器检索第二数据。 控制器从高速缓冲存储器复制第一数据，并且在系统时钟的不同于一个或多个第一时钟周期的第二时钟周期期间将第一数据存储在单端口存储器中的地址处。

    Efficient arithimetic logic units
    4.
    发明授权
    Efficient arithimetic logic units 有权
    高效的仿生逻辑单元

    公开(公告)号：US09098262B2

    公开(公告)日：2015-08-04

    申请号：US14529331

    申请日：2014-10-31

    Applicant: Juniper Networks, Inc.

    Inventor： Jean-Marc Frailong ,  Pradeep S. Sindhu ,  Jeffrey G. Libby ,  Jian Hui Huang ,  Rajesh Nair ,  John Keen

    IPC: G06F9/28 ,  G06F15/00 ,  G06F9/30

    CPC classification number: G06F9/28 ,  G06F7/57 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3859 ,  G06F9/3893 ,  G06F15/00

    Abstract: A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a first result, and output the result. The main arithmetic logic unit may select input buses among a plurality of data buses that carry the first result from the conditional arithmetic logic unit, perform a second arithmetic logic operation on data provided by the selected input buses to generate a second result, and write the second result in a storage component.

    Abstract translation: 处理器可以包括条件算术逻辑单元和主算术逻辑单元。 条件算术逻辑单元可以执行第一算术逻辑运算以产生第一结果，并输出结果。 主算术逻辑单元可以选择携带来自条件算术逻辑单元的第一结果的多个数据总线中的输入总线，对由所选择的输入总线提供的数据执行第二运算逻辑运算以产生第二结果，并写入 第二个结果是存储组件。

    Methods and apparatus for clock gating processing modules based on hierarchy and workload
    5.
    发明授权
    Methods and apparatus for clock gating processing modules based on hierarchy and workload 有权

    公开(公告)号：US09880603B1

    公开(公告)日：2018-01-30

    申请号：US13799234

    申请日：2013-03-13

    Applicant: Juniper Networks, Inc.

    Inventor： Vaishali Kulkarni ,  Jeffrey G. Libby ,  David J. Ofelt

    IPC: G06F1/00 ,  G06F1/32

    CPC classification number: G06F1/32 ,  G06F1/3228 ,  G06F1/3237 ,  G06F9/46

    Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to a first processing module and a second processing module. The first processing module has a priority higher than a priority of the second processing module. The dispatch module includes a workload counter associated with the first processing module to provide an indication of a workload at the first processing module. The dispatch module initiates a clock signal at the second processing module only if the indication of the workload at the first processing module satisfies a criterion. The dispatch module sends a data unit to the second processing module for processing only if the indication of the workload at the first processing module satisfies a criterion.

Patent Agency Ranking