公开(公告)号：US09116814B1

公开(公告)日：2015-08-25

申请号：US14092072

申请日：2013-11-27

Applicant: JUNIPER NETWORKS, INC.

Inventor： Jianhui Huang ,  Sharada Yeluri ,  Jean-Marc Frailong ,  Jeffrey G. Libby ,  Anurag P. Gupta ,  Paul Coelho

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0855 ,  G06F12/0815 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/12 ,  Y02D10/13

Abstract: A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.

Abstract translation: 数据读/写系统包括系统时钟，单端口存储器，与单端口存储器分开的高速缓存存储器，以及耦合到指令流水线的控制器。 控制器经由指令流水线接收第一数据以写入单端口存储器的地址，并且经由指令流水线接收从单端口存储器读取第二数据的请求。 控制器将第一数据存储在高速缓冲存储器中，并且在系统时钟的一个或多个第一时钟周期期间从高速缓冲存储器或单端口存储器检索第二数据。 控制器从高速缓冲存储器复制第一数据，并且在系统时钟的不同于一个或多个第一时钟周期的第二时钟周期期间将第一数据存储在单端口存储器中的地址处。