-
1.发明授权Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules 有权用于限制多个当前变化的方法和装置，同时时钟选通以管理处理器模块的功耗公开(公告)号：US09477257B1
公开(公告)日：2016-10-25
申请号：US13799210
申请日：2013-03-13
Applicant: Juniper Networks, Inc.
Inventor： Vaishali Kulkarni , Jeffrey G. Libby , Mihir Wagh
CPC classification number: G06F1/08 , G06F1/04 , G06F1/26 , G06F1/3225 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F3/0634 , G06F9/4881 , Y02D10/128 , Y02D10/14 , Y02D10/171
Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to multiple processing modules, each having a first clock configuration and a second clock configuration. The dispatch module, at a first time, changes a first processing module included in the multiple processing modules from a first clock configuration to a second clock configuration. The dispatch module prohibits, at a second time within a predetermined time period and after the first time, a second processing module included in the multiple processing modules from changing from the first clock configuration to the second clock configuration if an indicator associated with a number of changes of the multiple processing modules between a first clock configuration and a second clock configuration within the predetermined time period and prior to the second time satisfies a criterion.
Abstract translation: 在存储器或处理设备中的至少一个中实现的调度模块可操作地耦合到多个处理模块，每个处理模块具有第一时钟配置和第二时钟配置。 调度模块首次将包括在多个处理模块中的第一处理模块从第一时钟配置改变为第二时钟配置。 调度模块在预定时间段内和第一次之后的第二时间禁止包括在多个处理模块中的第二处理模块从第一时钟配置改变为第二时钟配置，如果与多个处理模块相关联的指示符 在第一时钟配置和第二时钟配置之间的多个处理模块在预定时间段内和第二时间之间的改变满足标准。
-
2.发明授权公开(公告)号：US10571988B1
公开(公告)日：2020-02-25
申请号：US15866664
申请日：2018-01-10
Applicant: Juniper Networks, Inc.
Inventor： Vaishali Kulkarni , Jeffrey G. Libby , David J. Ofelt
Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to a first processing module and a second processing module. The first processing module has a priority higher than a priority of the second processing module. The dispatch module includes a workload counter associated with the first processing module to provide an indication of a workload at the first processing module. The dispatch module initiates a clock signal at the second processing module only if the indication of the workload at the first processing module satisfies a criterion. The dispatch module sends a data unit to the second processing module for processing only if the indication of the workload at the first processing module satisfies a criterion.
-
3.发明授权公开(公告)号：US09880603B1
公开(公告)日：2018-01-30
申请号：US13799234
申请日：2013-03-13
Applicant: Juniper Networks, Inc.
Inventor： Vaishali Kulkarni , Jeffrey G. Libby , David J. Ofelt
CPC classification number: G06F1/32 , G06F1/3228 , G06F1/3237 , G06F9/46
Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to a first processing module and a second processing module. The first processing module has a priority higher than a priority of the second processing module. The dispatch module includes a workload counter associated with the first processing module to provide an indication of a workload at the first processing module. The dispatch module initiates a clock signal at the second processing module only if the indication of the workload at the first processing module satisfies a criterion. The dispatch module sends a data unit to the second processing module for processing only if the indication of the workload at the first processing module satisfies a criterion.
-
公开(公告)号：US09753524B1
公开(公告)日：2017-09-05
申请号：US15274548
申请日：2016-09-23
Applicant: Juniper Networks, Inc.
Inventor： Vaishali Kulkarni , Jeffrey G. Libby , Mihir Wagh
CPC classification number: G06F1/08 , G06F1/04 , G06F1/26 , G06F1/3225 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F3/0634 , G06F9/4881 , Y02D10/128 , Y02D10/14 , Y02D10/171
Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to multiple processing modules, each having a first clock configuration and a second clock configuration. The dispatch module, at a first time, changes a first processing module included in the multiple processing modules from a first clock configuration to a second clock configuration. The dispatch module prohibits, at a second time within a predetermined time period and after the first time, a second processing module included in the multiple processing modules from changing from the first clock configuration to the second clock configuration if an indicator associated with a number of changes of the multiple processing modules between a first clock configuration and a second clock configuration within the predetermined time period and prior to the second time satisfies a criterion.
-
-
-
Search Results
4
records
(took 0.011 seconds)
