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    FREQUENCY DETERMINATION ACROSS AN INTERFACE OF A DATA PROCESSING SYSTEM
    4.
    发明申请
    FREQUENCY DETERMINATION ACROSS AN INTERFACE OF A DATA PROCESSING SYSTEM 有权
    通过数据处理系统的接口进行频率确定

    公开(公告)号：US20150178209A1

    公开(公告)日：2015-06-25

    申请号：US14311476

    申请日：2014-06-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： JOHN T. HOLLAWAY, JR. ,  CHARLES F. MARINO ,  PRAVEEN S. REDDY

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0833 ,  G06F1/04 ,  G06F1/12 ,  G06F1/324 ,  G06F12/0831 ,  G06F13/1652 ,  G06F2212/62 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

    摘要： One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit is configured to be coupled to an interconnect of a multiprocessor system and is configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.

    摘要翻译： 所描述的一个或多个系统，设备，方法和/或处理可以确定处理器单元的最大高速缓存命令速率。 例如，处理器单元的接口被配置为耦合到多处理器系统的互连，并且被配置为使得接口的第一部分向接口的第二部分提供信号，其中接口的第一部分 利用已知频率进行操作，并且接口的第二部分利用处理器单元的高速缓存频率进行操作; 接口的第二部分循环信号; 接口的第一部分从接口的第二部分接收信号; 接口的第一部分基于已知频率，高速缓存的频率和信号来确定高速缓存命令速率; 并且该接口提供指示互连的高速缓存命令速率的信息。

    COMMAND RATE CONFIGURATION IN DATA PROCESSING SYSTEM
    5.
    发明申请
    COMMAND RATE CONFIGURATION IN DATA PROCESSING SYSTEM 有权
    数据处理系统中的指令速率配置

    公开(公告)号：US20150178238A1

    公开(公告)日：2015-06-25

    申请号：US14136818

    申请日：2013-12-20

    申请人： International Business Machines Corporation

    发明人： GUY L. GUTHRIE ,  DAVID J. KROLAK ,  CHARLES F. MARINO ,  PRAVEEN S. REDDY ,  MICHAEL S. SIEGEL

    IPC分类号： G06F13/42 ,  G06F9/54

    CPC分类号： G06F13/4208 ,  G06F3/00 ,  G06F9/54 ,  G06F13/36 ,  G06F13/4022 ,  G06F15/00 ,  Y02D10/14 ,  Y02D10/151

    摘要： In one or more embodiments, one or more systems, devices, methods, and/or processes described can continually increase a command rate of an interconnect if one or more requests to lower the command rate are not received within one or more periods of time. In one example, the command rate can be set to a fastest level. In another example, the command rate can be incrementally increased over periods of time. If a request to lower the command rate is received, the command rate can be set to a reference level or can be decremented to one slower rate level. In one or more embodiments, the one or more requests to lower the command rate can be based on at least one of an issue rate of speculative commands and a number of overcommit failures, among others.

    摘要翻译： 在一个或多个实施例中，如果在一个或多个时间段内没有接收到降低命令速率的一个或多个请求，则所描述的一个或多个系统，设备，方法和/或处理可以连续地增加互连的命令速率。 在一个示例中，命令速率可以设置为最快的级别。 在另一个示例中，命令速率可以在一段时间内递增地增加。 如果接收到降低命令速率的请求，则可以将命令速率设置为参考级别，或者可以减小到一个较慢的速率级别。 在一个或多个实施例中，降低命令速率的一个或多个请求可以基于以下中的至少一个：推测命令的发布率和多余的过度提供故障等。

    DETERMINING COMMAND RATE BASED ON DROPPED COMMANDS
    7.
    发明申请
    DETERMINING COMMAND RATE BASED ON DROPPED COMMANDS 有权
    基于剔除命令确定命令速率

    公开(公告)号：US20150178230A1

    公开(公告)日：2015-06-25

    申请号：US14136958

    申请日：2013-12-20

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： PAUL A. GANFIELD ,  GUY L. GUTHRIE ,  JOHN T. HOLLAWAY, JR. ,  DAVID J. KROLAK ,  CHARLES F. MARINO ,  PRAVEEN S. REDDY ,  MICHAEL S. SIEGEL ,  WILLIAM J. STARKE ,  JEFFREY A. STUECHELI

    IPC分类号： G06F13/36 ,  G06F13/40

    CPC分类号： G06F13/36 ,  G01R31/08 ,  G06F3/00 ,  G06F13/4068 ,  Y02D10/14 ,  Y02D10/151

    摘要： In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.

    摘要翻译： 在一个或多个实施例中，所描述的一个或多个系统，设备，方法和/或处理可以经由互连将速率主控命令发送到多个处理节点中的至少一个; 确定接收到与速率主命令相关联的指示丢弃命令的消息; 确定与丢弃的命令相关联的计数满足阈值; 并且响应于确定所述计数满足所述阈值，经由所述互连件向所述处理节点提供指示命令速率的信号。 此外，可以响应于确定接收到消息而增加计数。 多个处理节点中的至少一个可以经由互连接收指示命令速率的信号，并且可以经由互连来发出推测命令中的命令速率。

    FREQUENCY DETERMINATION ACROSS AN INTERFACE OF A DATA PROCESSING SYSTEM
    8.
    发明申请
    FREQUENCY DETERMINATION ACROSS AN INTERFACE OF A DATA PROCESSING SYSTEM 有权
    通过数据处理系统的接口进行频率确定

    公开(公告)号：US20150178208A1

    公开(公告)日：2015-06-25

    申请号：US14137127

    申请日：2013-12-20

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： JOHN T. HOLLAWAY, JR. ,  CHARLES F. MARINO ,  PRAVEEN S. REDDY

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0833 ,  G06F1/04 ,  G06F1/12 ,  G06F1/324 ,  G06F12/0831 ,  G06F13/1652 ,  G06F2212/62 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

    摘要： One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit configured to be coupled to an interconnect of a multiprocessor system and configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.

    摘要翻译： 所描述的一个或多个系统，设备，方法和/或处理可以确定处理器单元的最大高速缓存命令速率。 例如，处理器单元的接口被配置为耦合到多处理器系统的互连并且被配置为使得接口的第一部分向接口的第二部分提供信号，其中接口的第一部分利用 已知频率，并且接口的第二部分利用处理器单元的高速缓存频率进行操作; 接口的第二部分循环信号; 接口的第一部分从接口的第二部分接收信号; 接口的第一部分基于已知频率，高速缓存的频率和信号来确定高速缓存命令速率; 并且该接口提供指示互连的高速缓存命令速率的信息。