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公开(公告)号:US20180095905A1
公开(公告)日:2018-04-05
申请号:US15723949
申请日:2017-10-03
发明人: LAKSHMINARAYANA BABA ARIMILLI , YIFTACH BENJAMINI , BARTHOLOMEW BLANER , DANIEL M. DREPS , JOHN DAVID IRISH , DAVID J. KROLAK , LONNY LAMBRECHT , MICHAEL S. SIEGEL , WILLIAM J. STARKE , JEFFREY A. STUECHELI , KENNETH M. VALK , CURTIS C. WOLLBRINK
CPC分类号: G06F13/1626 , G06F3/061 , G06F3/0611 , G06F13/1673 , G06F13/4282 , G06F13/4291 , G06F2003/0691
摘要: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.
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公开(公告)号:US20190188138A1
公开(公告)日:2019-06-20
申请号:US15846392
申请日:2017-12-19
IPC分类号: G06F12/0831 , G06F13/16
CPC分类号: G06F12/0831 , G06F13/1663 , G06F2212/1032 , G06F2212/507
摘要: A data processing system includes first and second processing nodes and response logic coupled by an interconnect fabric. A first coherence participant in the first processing node is configured to issue a memory access request specifying a target memory block, and a second coherence participant in the second processing node is configured to issue a probe request regarding a memory region tracked in a memory coherence directory. The first coherence participant is configured to, responsive to receiving the probe request after the memory access request and before receiving a systemwide coherence response for the memory access request, detect an address collision between the probe request and the memory access request and, responsive thereto, transmit a speculative coherence response. The response logic is configured to, responsive to the speculative coherence response, provide a systemwide coherence response for the probe request that prevents the probe request from succeeding.
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公开(公告)号:US20150178239A1
公开(公告)日:2015-06-25
申请号:US14311508
申请日:2014-06-23
CPC分类号: G06F13/4208 , G06F3/00 , G06F9/54 , G06F13/36 , G06F13/4022 , G06F15/00 , Y02D10/14 , Y02D10/151
摘要: In one or more embodiments, one or more systems, devices, methods, and/or processes described can continually increase a command rate of an interconnect if one or more requests to lower the command rate are not received within one or more periods of time. In one example, the command rate can be set to a fastest level. In another example, the command rate can be incrementally increased over periods of time. If a request to lower the command rate is received, the command rate can be set to a reference level or can be decremented to one slower rate level. In one or more embodiments, the one or more requests to lower the command rate can be based on at least one of an issue rate of speculative commands and a number of overcommit failures, among others.
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公开(公告)号:US20150178238A1
公开(公告)日:2015-06-25
申请号:US14136818
申请日:2013-12-20
CPC分类号: G06F13/4208 , G06F3/00 , G06F9/54 , G06F13/36 , G06F13/4022 , G06F15/00 , Y02D10/14 , Y02D10/151
摘要: In one or more embodiments, one or more systems, devices, methods, and/or processes described can continually increase a command rate of an interconnect if one or more requests to lower the command rate are not received within one or more periods of time. In one example, the command rate can be set to a fastest level. In another example, the command rate can be incrementally increased over periods of time. If a request to lower the command rate is received, the command rate can be set to a reference level or can be decremented to one slower rate level. In one or more embodiments, the one or more requests to lower the command rate can be based on at least one of an issue rate of speculative commands and a number of overcommit failures, among others.
摘要翻译: 在一个或多个实施例中,如果在一个或多个时间段内没有接收到降低命令速率的一个或多个请求,则所描述的一个或多个系统,设备,方法和/或处理可以连续地增加互连的命令速率。 在一个示例中,命令速率可以设置为最快的级别。 在另一个示例中,命令速率可以在一段时间内递增地增加。 如果接收到降低命令速率的请求,则可以将命令速率设置为参考级别,或者可以减小到一个较慢的速率级别。 在一个或多个实施例中,降低命令速率的一个或多个请求可以基于以下中的至少一个:推测命令的发布率和多余的过度提供故障等。
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公开(公告)号:US20150178231A1
公开(公告)日:2015-06-25
申请号:US14311467
申请日:2014-06-23
发明人: PAUL A. GANFIELD , GUY L. GUTHRIE , JOHN T. HOLLAWAY, Jr. , DAVID J. KROLAK , CHARLES F. MARINO , PRAVEEN S. REDDY , MICHAEL S. SIEGEL , WILLIAM J. STARKE , JEFFREY A. STUECHELI
CPC分类号: G06F13/36 , G01R31/08 , G06F3/00 , G06F13/4068 , Y02D10/14 , Y02D10/151
摘要: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.
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公开(公告)号:US20150178230A1
公开(公告)日:2015-06-25
申请号:US14136958
申请日:2013-12-20
发明人: PAUL A. GANFIELD , GUY L. GUTHRIE , JOHN T. HOLLAWAY, JR. , DAVID J. KROLAK , CHARLES F. MARINO , PRAVEEN S. REDDY , MICHAEL S. SIEGEL , WILLIAM J. STARKE , JEFFREY A. STUECHELI
CPC分类号: G06F13/36 , G01R31/08 , G06F3/00 , G06F13/4068 , Y02D10/14 , Y02D10/151
摘要: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.
摘要翻译: 在一个或多个实施例中,所描述的一个或多个系统,设备,方法和/或处理可以经由互连将速率主控命令发送到多个处理节点中的至少一个; 确定接收到与速率主命令相关联的指示丢弃命令的消息; 确定与丢弃的命令相关联的计数满足阈值; 并且响应于确定所述计数满足所述阈值,经由所述互连件向所述处理节点提供指示命令速率的信号。 此外,可以响应于确定接收到消息而增加计数。 多个处理节点中的至少一个可以经由互连接收指示命令速率的信号,并且可以经由互连来发出推测命令中的命令速率。
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