公开(公告)号：US20190042486A1

公开(公告)日：2019-02-07

申请号：US15667270

申请日：2017-08-02

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： GUY L. GUTHRIE ,  CHARLES MARINO ,  PRAVEEN S. REDDY

IPC分类号： G06F13/16 ,  G06F12/0813 ,  G06F12/0811

摘要： A technique for operating a data processing system includes determining, by an arbiter of a processing unit of the data processing system, whether an over-commit has occurred. In response to determining that the over-commit has occurred, the arbiter selects a broadcast command to be dropped based on a number of hops traversed through the data processing system by the broadcast command.

公开(公告)号：US20140365733A1

公开(公告)日：2014-12-11

申请号：US14465516

申请日：2014-08-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： BARTHOLOMEW BLANER ,  CHARLES MARINO ,  MICHAEL S. SIEGEL ,  WILLIAM J. STARKE ,  JEFF A. STUECHELI

IPC分类号： G06F12/08

CPC分类号： G06F12/0822 ,  G06F12/0831 ,  G06F2212/622

摘要： An integrated circuit system including a first integrated circuit chip including first logic, a second integrated circuit chip, and second logic distributed across the first and second integrated circuit chips. The second logic includes a first unit integrated in the first integrated circuit chip and a second unit integrated in the second integrated circuit chip. The integrated circuit system further includes a physical communication link coupling the first unit in the first integrated circuit chip and the second unit in the second integrated circuit chip and a request interface between the first logic and first unit of the second logic. The request interface is implemented in the first integrated circuit such that communication via the request interface between the first logic and the first unit of the second logic has low latency and such that the request interface is decoupled from the physical communication link.

摘要翻译： 一种集成电路系统，包括第一集成电路芯片，包括第一逻辑，第二集成电路芯片和分布在第一和第二集成电路芯片上的第二逻辑。 第二逻辑包括集成在第一集成电路芯片中的第一单元和集成在第二集成电路芯片中的第二单元。 集成电路系统还包括耦合第一集成电路芯片中的第一单元和第二集成电路芯片中的第二单元的物理通信链路以及第二逻辑的第一逻辑与第一单元之间的请求接口。 请求接口在第一集成电路中实现，使得经由第一逻辑和第二逻辑的第一单元之间的请求接口的通信具有低等待时间，并且使得请求接口与物理通信链路分离。

公开(公告)号：US20190042342A1

公开(公告)日：2019-02-07

申请号：US15667313

申请日：2017-08-02

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： GUY L. GUTHRIE ,  CHARLES MARINO ,  PRAVEEN S. REDDY ,  MICHAEL S. SIEGEL

IPC分类号： G06F11/07

CPC分类号： G06F11/076 ,  G06F11/0757 ,  G06F11/0784 ,  G06F11/0793

摘要： A technique for operating a data processing system includes detecting that a processing unit within a first group of processing units in the data processing system has a hang condition. In response to detecting that the processing unit has a hang condition, a command issue rate for the first group of processing units is reduced. One or more other groups of processing units in the data processing system are notified that the first group of processing units has reduced the command issue rate for the first group of processing units. In response to the notifying, respective command issue rates of the other groups of processing units are reduced to reduce a number of commands received by the first group of processing units from the other groups of processing units.

公开(公告)号：US20140149689A1

公开(公告)日：2014-05-29

申请号：US13777847

申请日：2013-02-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： BARTHOLOMEW BLANER ,  CHARLES MARINO ,  MICHAEL S. SIEGEL ,  WILLIAM J. STARKE ,  JEFF A. STUECHELI

IPC分类号： G06F12/08

CPC分类号： G06F12/0822 ,  G06F12/0831 ,  G06F2212/622

摘要： A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request from an attached processor (AP) and an expected coherence state of a target address of the memory access request with respect to a cache memory of the AP. In response, the CAPP determines a coherence state of the target address and whether or not the expected state matches the determined coherence state. In response to determining that the expected state matches the determined coherence state, the CAPP issues a memory access request corresponding to that received from the AP on a system fabric of the primary coherent system. In response to determining that the expected state does not match the coherence state determined by the CAPP, the CAPP transmits a failure message to the AP without issuing on the system fabric a memory access request corresponding to that received from the AP.

公开(公告)号：US20140149681A1

公开(公告)日：2014-05-29

申请号：US13686489

申请日：2012-11-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： BARTHOLOMEW BLANER ,  CHARLES MARINO ,  MICHAEL S. SIEGEL ,  WILLIAM J. STARKE ,  JEFF A. STUECHELI

IPC分类号： G06F12/08

CPC分类号： G06F12/0822 ,  G06F12/0831 ,  G06F2212/622

摘要： A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request from an attached processor (AP) and an expected coherence state of a target address of the memory access request with respect to a cache memory of the AP. In response, the CAPP determines a coherence state of the target address and whether or not the expected state matches the determined coherence state. In response to determining that the expected state matches the determined coherence state, the CAPP issues a memory access request corresponding to that received from the AP on a system fabric of the primary coherent system. In response to determining that the expected state does not match the coherence state determined by the CAPP, the CAPP transmits a failure message to the AP without issuing on the system fabric a memory access request corresponding to that received from the AP.

摘要翻译： 主相干系统的相干连接处理器代理（CAPP）相对于AP的高速缓冲存储器接收来自附加处理器（AP）的存储器访问请求和存储器访问请求的目标地址的预期相干状态。 作为响应，CAPP确定目标地址的相干状态以及预期状态是否与所确定的相干状态相匹配。 响应于确定预期状态与确定的相干状态匹配，CAPP发出与在主要相干系统的系统结构上从AP接收的存储器访问请求相对应的存储器访问请求。 响应于确定预期状态与由CAPP确定的相干状态不匹配，CAPP向AP发送故障消息，而不在系统结构上发出与从AP接收到的对应的存储器访问请求。