公开(公告)号：US10410081B2

公开(公告)日：2019-09-10

申请号：US14581701

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Subramaniam Maiyuran ,  Thomas A. Piazza ,  Jorge F. Garcia Pabon ,  Shubh B. Shah

IPC: G06K9/46 ,  G06T15/00

Abstract: An apparatus and method are described for a high throughput rasterizer. For example, one embodiment of an apparatus comprises: block selection logic to select a plurality of pixel blocks associated with edges of a primitive, the plurality of pixel blocks selected based on the pixel blocks having samples which are both inside and outside of the primitive; and edge determination logic to analyze samples of the plurality of pixel blocks selected by the block selection logic and responsively generate data identifying each edge of the primitive; and final mask determination logic to combine the data identifying each edge and generate a final mask representing the primitive.

公开(公告)号：US09824412B2

公开(公告)日：2017-11-21

申请号：US14494653

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Subramaniam Maiyuran ,  Thomas A. Piazza ,  Kalyan K. Bhiravabhatla ,  Peter L. Doyle ,  Paul A. Johnson ,  Bimal Poddar ,  Jon N. Hasselgren ,  Carl J. Munkberg ,  Tomas G. Akenine-Moller ,  Harri Syrja ,  Kevin Rogovin ,  Robert L. Farrell

IPC: G06T15/40 ,  G06T1/20 ,  G06T15/50 ,  G09G5/393

CPC classification number: G06T1/20 ,  G06T15/40 ,  G06T15/405 ,  G06T15/503 ,  G09G5/393

Abstract: In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.

公开(公告)号：US10204051B2

公开(公告)日：2019-02-12

申请号：US15393907

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Zeev Offen ,  Ariel Berkovits ,  Thomas A. Piazza ,  Robert L. Farrell ,  Altug Koker ,  Opher Kahn

IPC: G09G5/36 ,  G06F12/0831 ,  G06F12/0817 ,  G06F12/0811 ,  G06T1/60 ,  G06F13/42 ,  G11C7/10 ,  G06F13/16 ,  G06F13/28

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：US09665488B2

公开(公告)日：2017-05-30

申请号：US14158865

申请日：2014-01-20

Applicant: Intel Corporation

Inventor： Zeev Offen ,  Ariel Berkovits ,  Thomas A. Piazza ,  Robert Farrell ,  Altug Koker ,  Opher Kahn

IPC: G06T9/00 ,  G06F12/0831 ,  G06F12/0817 ,  G06F12/0811 ,  G06T1/60

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0828 ,  G06F12/0835 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4282 ,  G06F2212/283 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2213/0026 ,  G06T1/60 ,  G11C7/1072

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：US20170109304A1

公开(公告)日：2017-04-20

申请号：US15393921

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Zeev Offen ,  Ariel Berkovits ,  Thomas A. Piazza ,  Robert L. Farrell ,  Altug Koker ,  Opher Kahn

IPC: G06F13/28 ,  G06F13/16 ,  G06F12/0817 ,  G06F13/42 ,  G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0828 ,  G06F12/0835 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4282 ,  G06F2212/283 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2213/0026 ,  G06T1/60 ,  G11C7/1072

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：US20170109280A1

公开(公告)日：2017-04-20

申请号：US15393883

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Zeev Offen ,  Ariel Berkovits ,  Thomas A. Piazza ,  Robert L. Farrell ,  Altug Koker ,  Opher Kahn

IPC: G06F12/0811 ,  G06F13/42 ,  G06F12/0831

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0828 ,  G06F12/0835 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4282 ,  G06F2212/283 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2213/0026 ,  G06T1/60 ,  G11C7/1072

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：US09087392B2

公开(公告)日：2015-07-21

申请号：US13627699

申请日：2012-09-26

Applicant: Intel Corporation

Inventor： Peter L. Doyle ,  Thomas A. Piazza

IPC: G06T1/60 ,  G06T15/00 ,  G06T17/20

CPC classification number: G06T1/60 ,  G06T15/005 ,  G06T17/20

Abstract: An apparatus may include a memory to store a set of triangle vertices in a triangle, a processor circuit coupled to the memory and a cache to cache a set of triangle vertex indices corresponding to triangle vertices most recently transmitted through a graphics pipeline. The apparatus may also include an autostrip vertex processing component operative on the processor circuit to receive from the memory the set of triangle vertices, compare an index for each vertex of the set of triangle vertices to determine matches to the set of cached triangle vertex indices, and shift a single vertex index into the cache, the single vertex index corresponding to a vertex miss in which a given vertex of the set of triangle vertices does not match any vertex index of the set of cached triangle vertex indices when exactly two matches to the set of cached triangle vertex indices are found.

Abstract translation: 装置可以包括存储器，用于存储三角形中的一组三角形顶点，耦合到存储器的处理器电路和高速缓存，以缓存对应于最近通过图形管线传输的三角形顶点的一组三角形顶点索引。 该装置还可以包括在处理器电路上操作以从存储器接收该组三角形顶点的自动条带顶点处理组件，比较该组三角形顶点的每个顶点的索引，以确定与该组缓存的三角形顶点索引的匹配， 并将单个顶点索引移动到高速缓存中，对应于顶点未​​命中的单个顶点索引，其中三角形顶点集合的给定顶点与该组高速缓存的三角形顶点索引的任何顶点索引不匹配，当恰好两个匹配时 找到一组缓存的三角形顶点索引。

公开(公告)号：US10078590B2

公开(公告)日：2018-09-18

申请号：US15393883

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Zeev Offen ,  Ariel Berkovits ,  Thomas A. Piazza ,  Robert L. Farrell ,  Altug Koker ,  Opher Kahn

IPC: G06T9/00 ,  G06F12/0831 ,  G06F12/0817 ,  G06F12/0811 ,  G06T1/60 ,  G06F13/42 ,  G11C7/10 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0828 ,  G06F12/0835 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4282 ,  G06F2212/283 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2213/0026 ,  G06T1/60 ,  G11C7/1072

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：US09928170B2

公开(公告)日：2018-03-27

申请号：US15264045

申请日：2016-09-13

Applicant: Intel Corporation

Inventor： Altug Koker ,  Thomas A. Piazza ,  Murali Sundaresan

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0846 ,  G06F12/0853

CPC classification number: G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0875 ,  G06F12/128 ,  G06F2212/621

Abstract: In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques.

公开(公告)号：US09741154B2

公开(公告)日：2017-08-22

申请号：US13682967

申请日：2012-11-21

Applicant: Intel Corporation

Inventor： Thomas A. Piazza ,  Bimal Poddar ,  Peter L. Doyle

IPC: G06T15/00 ,  G06T15/40

CPC classification number: G06T15/005 ,  G06T15/40

Abstract: According to some embodiments of the present invention, pixel throughput may be improved by performing depth tests and recording the results on the granularity of an input geometry object. An input geometry object is any object within the depiction represented by a primitive, such as a triangle within an input triangle list or a patch within an input patch list.