公开(公告)号：US11437346B2

公开(公告)日：2022-09-06

申请号：US16025710

申请日：2018-07-02

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Leigh E. Wojewoda ,  Mathew Manusharow ,  Siddharth Kulasekaran

IPC: H01L21/00 ,  H01L23/34 ,  H01L25/065 ,  H01L49/02 ,  H01F27/08 ,  H01L23/64

Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein the inductor is at least partially embedded within the substrate. One or more thermal vent structures extend through at least one of the substrate or a board attached to the substrate. The one or more thermal vent structures provide a thermal pathway for cooling for the inductor.

公开(公告)号：US12224252B2

公开(公告)日：2025-02-11

申请号：US17030121

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  William J. Lambert ,  Haifa Hariri ,  Siddharth Kulasekaran ,  Mathew Manusharow ,  Anne Augustine

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552

Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.

公开(公告)号：US10651525B2

公开(公告)日：2020-05-12

申请号：US15997644

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/06 ,  H01P3/02 ,  H05K1/02 ,  H01P3/08

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20200006250A1

公开(公告)日：2020-01-02

申请号：US16024007

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Mathew Manusharow ,  Beomseok Choi ,  Digvijay Raorane

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/64 ,  H01L25/18 ,  H01F27/28 ,  H01F38/14 ,  G06F1/28

Abstract: An apparatus may include a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to one or more sides of the substrate. One or more sections of the stiffener may include a magnetic material. The apparatus may further include an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material.

公开(公告)号：US11791528B2

公开(公告)日：2023-10-17

申请号：US17714957

申请日：2022-04-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

CPC classification number: H01P3/082 ,  H01P3/02 ,  H01P3/026 ,  H01P3/06 ,  H01P3/08 ,  H01P3/085 ,  H01P3/088 ,  H05K1/0245

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US11688729B2

公开(公告)日：2023-06-27

申请号：US16030196

申请日：2018-07-09

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Krishna Bharath ,  Mathew Manusharow

IPC: H01L27/01 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L27/016 ,  H01L23/49816 ,  H01L23/49827 ,  H01L28/87 ,  H01L28/91

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US11527489B2

公开(公告)日：2022-12-13

申请号：US16024007

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Mathew Manusharow ,  Beomseok Choi ,  Digvijay Raorane

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/64 ,  G06F1/28 ,  H01F27/28 ,  H01F38/14 ,  H01L25/18

Abstract: An apparatus includes a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to the substrate. One or more sections of the stiffener may includes a magnetic material. The apparatus further includes an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material. In some examples where a first coil is wrapped around a first section of the stiffener, and a second coil is wrapped around a second section of the stiffener, current supplied to the first coil generates at the second coil a current that is further transmitted to the one or more semiconductor dies.

公开(公告)号：US11329358B2

公开(公告)日：2022-05-10

申请号：US16841072

申请日：2020-04-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20200013770A1

公开(公告)日：2020-01-09

申请号：US16030196

申请日：2018-07-09

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Krishna Bharath ,  Mathew Manusharow

IPC: H01L27/01 ,  H01L23/498 ,  H01L49/02

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200006166A1

公开(公告)日：2020-01-02

申请号：US16022152

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Digvijay Raorane ,  Mathew Manusharow

IPC: H01L23/13 ,  H01L23/64 ,  H01L23/15 ,  H01L23/498

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a package substrate; a stiffener having a surface, wherein the stiffener includes a cavity and a conductive pathway between the cavity and the surface of the stiffener, and wherein the stiffener is coupled to the package substrate such that the surface of the stiffener is between the cavity and the package substrate; and an electrical component, wherein the electrical component is embedded in the cavity and is electrically coupled to the package substrate via the conductive pathway.