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    MULTILAYER SUBSTRATE AND MANUFACTURING METHOD THEREFOR
    3.
    发明公开
    MULTILAYER SUBSTRATE AND MANUFACTURING METHOD THEREFOR 审中-公开

    公开(公告)号：US20230318160A1

    公开(公告)日：2023-10-05

    申请号：US18207169

    申请日：2023-06-08

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yushi SOETA ,  Kentarou KAWABE ,  Kouki SHIMIZU ,  Toru KURISU ,  Akihiro YAMAKAWA

    IPC: H01P3/08 ,  H05K1/09 ,  H05K1/05 ,  H05K3/46

    CPC classification number: H01P3/088 ,  H01P3/082 ,  H05K1/09 ,  H05K1/05 ,  H05K3/4644

    Abstract: A multilayer body has a structure including insulating layers stacked on each other in an up-down direction. A first conductive layer is on a top main surface of one of the insulating layers. A first signal is transmitted through the first conductive layer. A second conductive layer is on a same insulating layer that the first conductive layer is on. The second conductive layer is on a same main surface as the top main surface or the bottom main surface of the insulating layer on which the first conductive layer is located. A second signal having a higher frequency than the first signal is transmitted through the second conductive layer. A top conductive layer is above the second conductive layer. A thickness of the second conductive layer in the up-down direction is smaller than that of the first conductive layer in the up-down direction.

    MULTILAYER SUBSTRATE AND ELECTRONIC DEVICE
    4.
    发明公开
    MULTILAYER SUBSTRATE AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230299453A1

    公开(公告)日：2023-09-21

    申请号：US18201212

    申请日：2023-05-24

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Nobuo IKEMOTO ,  Kentarou KAWABE

    IPC: H01P3/08 ,  H05K1/02 ,  H05K1/14

    CPC classification number: H01P3/088 ,  H01P3/082 ,  H05K1/028 ,  H05K1/144 ,  H05K2201/095

    Abstract: A multilayer substrate includes layers stacked on each other in an up-down direction of a multilayer body. The layers include a first spacer, a first ground conductive layer above the first spacer, and a signal conductive layer that overlaps the first ground conductive layer and is located below the first spacer. First through-holes pass through the first spacer and are arranged along a first direction. A distance between centroids of first through-holes adjacent to each other in the first direction is uniform or substantially uniform. Sets of first through-holes are provided in the first spacer. Sets of first through-holes are arranged along a second direction. A distance between centroids of first through-holes adjacent to each other in the second direction is uniform or substantially uniform. At least one first through-hole is a first hollow through-hole overlapping the signal conductive layer.

    Compact impedance transformer
    9.
    发明授权
    Compact impedance transformer 有权

    公开(公告)号：US09779868B2

    公开(公告)日：2017-10-03

    申请号：US14701257

    申请日：2015-04-30

    Applicant: RF Micro Devices, Inc.

    Inventor： James Burr Hecht

    IPC: H01F27/34 ,  H01F19/04 ,  H03H7/38 ,  H01F27/28 ,  H03H7/42 ,  H03H7/01 ,  H01P3/08 ,  H01P5/02 ,  H01F27/40

    CPC classification number: H01F19/04 ,  H01F27/2804 ,  H01F27/34 ,  H01F27/40 ,  H01F2027/2809 ,  H01P3/082 ,  H01P5/028 ,  H03H7/0115 ,  H03H7/38 ,  H03H7/42 ,  H03H7/425

    Abstract: A compact impedance transformer is disclosed having a first dielectric substrate, a first planar conductor disposed on a top surface of the first dielectric substrate in a loop, a second planar conductor disposed on a bottom surface of the first dielectric substrate in a second loop, wherein the first planar conductor and the second planar conductor are substantially identical and in stacked alignment. A second dielectric substrate has a third planar conductor disposed on a top surface of the second dielectric substrate in a third loop, and a fourth planar conductor disposed on a bottom surface of the second dielectric substrate in a fourth loop, wherein the third planar conductor and the fourth planar conductor are substantially identical and in stacked alignment. An interconnect structure between terminals of the first planar conductor, the second planar conductor, the third planar conductor, and the fourth planar conductor provide impedance transformations.

    TRANSMISSION LINE CABLE
    10.
    发明申请
    TRANSMISSION LINE CABLE 审中-公开

    公开(公告)号：US20170194686A1

    公开(公告)日：2017-07-06

    申请号：US15465635

    申请日：2017-03-22

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Shingo ITO ,  Kuniaki YOSUI

    IPC: H01P3/02

    CPC classification number: H01P3/026 ,  H01P1/02 ,  H01P1/047 ,  H01P3/082 ,  H01P3/085 ,  H01P5/028 ,  H05K1/0245 ,  H05K1/142 ,  H05K2201/0919 ,  H05K2201/09845

    Abstract: A first signal conductor pattern, a first ground conductor pattern, and a second ground conductor pattern define a first transmission line with a strip line structure. A second signal conductor pattern, a third ground conductor pattern, and a fourth ground conductor pattern define a second transmission line with a strip line structure. A first connecting portion at an end of the first transmission line and a second connecting portion at an end of the second transmission line are stacked together so that the first ground conductor pattern is electrically connected to the third ground conductor pattern, the second ground conductor pattern is electrically connected to the fourth ground conductor pattern, and the first signal conductor pattern is electrically connected to the second signal conductor pattern.

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