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公开(公告)号：US20240188225A1
公开(公告)日：2024-06-06
申请号：US18060598
申请日：2022-12-01
申请人： Intel Corporation
CPC分类号： H05K3/4038 , C23C18/1868 , C23C18/38 , H05K1/0306 , H05K1/115 , H05K3/181 , H05K2201/09563 , H05K2201/2081 , H05K2203/107
摘要： A method for manufacturing a structured substrate is provided, the method including: forming a plurality of openings extending from a first surface of a substrate towards a second surface of the substrate, wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass, and wherein each of the openings comprises a sidewall; forming a first layer at least on the sidewall of the openings; forming a second layer on the first layer, wherein the second layer comprises titanium; and depositing metal on the second layer to at least partially fill the openings.
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公开(公告)号：US20240079530A1
公开(公告)日：2024-03-07
申请号：US17903126
申请日：2022-09-06
申请人： Intel Corporation
发明人： Jacob VEHONSKY , Onur OZKAN , Vinith BEJUGAM , Mao-Feng TSENG , Nicholas HAEHN , Andrea NICOLAS FLORES , Ali LEHAF , Benjamin DUONG , Joshua STACEY
CPC分类号： H01L33/486 , H01L33/005 , H01L33/60 , H01L33/62 , H01L2933/0058 , H01L2933/0066
摘要： Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.
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公开(公告)号：US20240215163A1
公开(公告)日：2024-06-27
申请号：US18089489
申请日：2022-12-27
申请人： Intel Corporation
发明人： Onur OZKAN , Jacob VEHONSKY , Vinith BEJUGAM , Nicholas S. HAEHN , Andrea NICOLAS FLORES , Mao-Feng TSENG
CPC分类号： H05K1/112 , H05K1/0306 , H05K1/183 , H01L23/49838
摘要： Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprise glass. In an embodiment, a via is provided through the substrate, where the via is electrically conductive. In an embodiment, a recess is formed into the first surface of the substrate, and a trace is embedded in the recess. In an embodiment, the trace is electrically conductive.
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公开(公告)号：US20240079259A1
公开(公告)日：2024-03-07
申请号：US17901894
申请日：2022-09-02
申请人： Intel Corporation
发明人： Jacob VEHONSKY , Onur OZKAN , Vinith BEJUGAM , Mao-Feng TSENG , Andrea NICOLAS , Nicholas HAEHN
CPC分类号： H01L21/6835 , B32B3/30 , B32B7/12 , B32B33/00 , B32B37/12 , H01L21/67121 , B32B17/06 , H01L2221/68345
摘要： The present disclosure is directed to a system that uses a dual surface substrate carrier that includes a first transparent support with a first top surface and first bottom surface, a second transparent support with a second top surface and second bottom surface, and a reflective film positioned between and attached to the first transparent support and the second transparent support. The first transparent support has a first set of trenches configured in the first top surface that form a first set of ridges between the plurality of trenches and the second transparent support has a second set of trenches configured in the second top surface that form a second set of ridges between the plurality of trenches. The first transparent support is also configured with a first build surface and the second transparent support is also configured with a second build surface that are platforms for building package substrates.
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