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    Scheduling and dispatch of GPGPU workloads
    3.
    发明授权
    Scheduling and dispatch of GPGPU workloads 有权

    公开(公告)号：US10937118B2

    公开(公告)日：2021-03-02

    申请号：US16260031

    申请日：2019-01-28

    Applicant: Intel Corporation

    Inventor： Jayanth N. Rao ,  Michal Mrozek

    IPC: G06T1/20 ,  G06F9/50

    Abstract: A method and system are described herein for an optimization technique on two aspects of thread scheduling and dispatch when the driver is allowed to pick the scheduling attributes. The present techniques rely on an enhanced GPGPU Walker hardware command and one dimensional local identification generation to maximize thread residency.

    Method and apparatus to facilitate shared pointers in a heterogeneous platform
    4.
    发明授权
    Method and apparatus to facilitate shared pointers in a heterogeneous platform 有权
    促进异构平台中共享指针的方法和装置

    公开(公告)号：US08862831B2

    公开(公告)日：2014-10-14

    申请号：US14020616

    申请日：2013-09-06

    Applicant: Intel Corporation

    Inventor： Yang Ni ,  Rajkishore Barik ,  Ali-Reza Adl-Tabatabai ,  Tatiana Shpeisman ,  Jayanth N. Rao ,  Ben J. Ashbaugh ,  Tomasz Janczak

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F15/167 ,  G06T1/60

    CPC classification number: G06F12/0806 ,  G06F15/167 ,  G06T1/60

    Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

    Abstract translation: 一种促进异构平台中的共享指针的方法和装置。 在本发明的一个实施例中，异构或非均匀平台包括但不限于中央处理核心或单元，图形处理核心或单元，数字信号处理器，接口模块和任何其他形式的 处理核心。 异构平台具有促进共享指向CPU和GPU共享的存储器的位置的逻辑。 通过在异构平台中共享指针，可以简化异构平台中不同核心之间的数据或信息共享。

    Scheduling and dispatch of GPGPU workloads
    5.
    发明授权
    Scheduling and dispatch of GPGPU workloads 有权

    公开(公告)号：US10235732B2

    公开(公告)日：2019-03-19

    申请号：US14142681

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Jayanth N. Rao ,  Michal Mrozek

    IPC: G06T1/20 ,  G06F9/50

    Abstract: A method and system are described herein for an optimization technique on two aspects of thread scheduling and dispatch when the driver is allowed to pick the scheduling attributes. The present techniques rely on an enhanced GPGPU Walker hardware command and one dimensional local identification generation to maximize thread residency.

    Facilitating dynamic pipelining of workload executions on graphics processing units on computing devices
    6.
    发明授权
    Facilitating dynamic pipelining of workload executions on graphics processing units on computing devices 有权

    公开(公告)号：US10068306B2

    公开(公告)日：2018-09-04

    申请号：US14574606

    申请日：2014-12-18

    Applicant: INTEL CORPORATION

    Inventor： Jayanth N. Rao ,  Pavan K. Lanka

    IPC: G06F9/50 ,  G06T1/20 ,  G06F9/46 ,  H03K99/00

    Abstract: A mechanism is described for facilitating dynamic pipelining of workload executions at graphics processing units on computing devices. A method of embodiments, as described herein, includes generating a command buffer having a plurality of kernels relating to a plurality of workloads to be executed at a graphics processing unit (GPU), and pipelining the workloads to be processed at the GPU, where pipelining includes scheduling each kernel to be executed on the GPU based on at least one of availability of resource threads and status of one or more dependency events relating to each kernel in relation to other kernels of the plurality of kernels.

    Aborting graphics processor workload execution
    7.
    发明授权
    Aborting graphics processor workload execution 有权

    公开(公告)号：US09892480B2

    公开(公告)日：2018-02-13

    申请号：US13929856

    申请日：2013-06-28

    Applicant: Intel Corporation

    Inventor： Jayanth N. Rao

    IPC: G06F15/80 ,  G06T1/20 ,  G06F9/48

    CPC classification number: G06T1/20 ,  G06F9/485

    Abstract: According to some embodiments, a graphics processor may abort a workload without requiring changes to the kernel code compilation or intruding upon graphics processing unit execution. Instead, it is possible to only read the predicate state once before starting and once before restarting a workload that has been preempted because the user wishes to abort the work. This avoids the need to read from each execution unit, reducing the drain on memory bandwidth and increasing power and performance in some embodiments.

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