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公开(公告)号：US11119838B2
公开(公告)日：2021-09-14
申请号：US16572382
申请日：2019-09-16
申请人： Intel Corporation
摘要： Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.
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公开(公告)号：US10417070B2
公开(公告)日：2019-09-17
申请号：US15687957
申请日：2017-08-28
申请人： Intel Corporation
摘要： Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.
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3.发明申请公开(公告)号：US20190258414A1
公开(公告)日：2019-08-22
申请号：US16405296
申请日：2019-05-07
申请人： Intel Corporation
摘要： Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.
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公开(公告)号：US20180039528A1
公开(公告)日：2018-02-08
申请号：US15687957
申请日：2017-08-28
申请人： Intel Corporation
CPC分类号： G06F11/073 , G06F11/0769 , G06F11/0787 , G09C1/00 , G11C5/04 , G11C29/52 , G11C2029/0409
摘要： Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.
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公开(公告)号：US10719443B2
公开(公告)日：2020-07-21
申请号：US16363992
申请日：2019-03-25
申请人： Intel Corporation
发明人： Raj K. Ramanujan , Rajat Agarwal , Kai Cheng , Taarinya Polepeddi , Camille C. Raad , David J. Zimmerman , Muthukumar P. Swaminathan , Dimitrios Ziakas , Mohan J. Kumar , Bassam N. Coury , Glenn J. Hinton
IPC分类号： G11C11/406 , G06F12/0811 , G06F12/0895 , G06F12/0897 , G11C14/00
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”
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6.发明授权公开(公告)号：US09817738B2
公开(公告)日：2017-11-14
申请号：US14845503
申请日：2015-09-04
申请人： Intel Corporation
CPC分类号： G06F11/3037 , G06F11/073 , G06F11/0793 , G06F11/1612 , G06F11/167 , G06F12/00 , G11C29/42 , G11C29/52 , G11C2029/0411
摘要： Systems and methods may provide for detecting that a read operation is directed to a memory region while the memory region is in a poisoned state and clearing the poisoned state if volatile data stored in the memory region does not correspond to a known data pattern. Additionally, the memory region may be maintained in the poisoned state if the volatile data stored in the memory region corresponds to the known data pattern. In one example, an error may be detected, wherein the error is associated with a write operation directed to the memory region. In such a case, the poisoned state may be set for the volatile data in response to the error and the known data pattern may be written to the memory region.
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7.发明授权公开(公告)号：US10915254B2
公开(公告)日：2021-02-09
申请号：US16405296
申请日：2019-05-07
申请人： Intel Corporation
IPC分类号： G06F3/06 , G06F12/02 , G06F12/0866 , G06F11/16 , G06F11/00 , G06F12/0888
摘要： Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.
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8.发明授权公开(公告)号：US10296238B2
公开(公告)日：2019-05-21
申请号：US14975160
申请日：2015-12-18
申请人： Intel Corporation
摘要： Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.
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公开(公告)号：US10241912B2
公开(公告)日：2019-03-26
申请号：US15457847
申请日：2017-03-13
申请人： Intel Corporation
发明人： Raj K. Ramanujan , Rajat Agarwal , Kai Cheng , Taarinya Polepeddi , Camille C. Raad , David J. Zimmerman , Muthukumar P. Swaminathan , Dimitrios Ziakas , Mohan J. Kumar , Bassam N. Coury , Glenn J. Hinton
IPC分类号： G06F13/12 , G06F13/38 , G06F12/0811 , G06F12/0897 , G11C11/406 , G11C14/00 , G06F12/0895
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”
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公开(公告)号：US09753793B2
公开(公告)日：2017-09-05
申请号：US14319387
申请日：2014-06-30
申请人： INTEL CORPORATION
CPC分类号： G06F11/073 , G06F11/0769 , G06F11/0787 , G09C1/00 , G11C5/04 , G11C29/52 , G11C2029/0409
摘要： Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.
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