Invention Grant
- Patent Title: Apparatus and method for implementing a multi-level memory hierarchy
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Application No.: US16363992Application Date: 2019-03-25
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Publication No.: US10719443B2Publication Date: 2020-07-21
- Inventor: Raj K. Ramanujan , Rajat Agarwal , Kai Cheng , Taarinya Polepeddi , Camille C. Raad , David J. Zimmerman , Muthukumar P. Swaminathan , Dimitrios Ziakas , Mohan J. Kumar , Bassam N. Coury , Glenn J. Hinton
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G11C11/406
- IPC: G11C11/406 ; G06F12/0811 ; G06F12/0895 ; G06F12/0897 ; G11C14/00

Abstract:
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”
Public/Granted literature
- US20190220406A1 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY Public/Granted day:2019-07-18
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