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    Fast and efficient storage system implemented with multiple cloud services
    1.
    发明授权
    Fast and efficient storage system implemented with multiple cloud services 有权

    公开(公告)号：US12124417B2

    公开(公告)日：2024-10-22

    申请号：US17156261

    申请日：2021-01-22

    申请人： SCALITY, S.A.

    发明人： Giorgio Regni ,  Vianney Rancurel ,  Nicolas Trangez

    IPC分类号： G06F16/182 ,  G06F16/11 ,  G06F16/16 ,  G06F16/18

    CPC分类号： G06F16/1824 ,  G06F16/128 ,  G06F16/164 ,  G06F16/1873

    摘要： A method for implementing a storage system is described. The method includes accepting a filepath from a user that specifies a file. The method includes forming a primary key for a representation of the file. The method includes applying the primary key to a database cloud service to obtain a representation of the file. The representation of the file includes an inode for the file's meta data. The method includes using the inode for the file's meta data to obtain the file's meta data from a high performance object cloud storage service. The file's meta data points to information within the high performance object cloud storage service for accessing the file's stripes. The method includes accessing the information within the high performance object cloud storage service to obtain an object ID for a stripe within the file. The method includes using the object ID to access the stripe from a low performance object cloud storage service.

    Memory hub providing cache coherency protocol system method for multiple processor sockets comprising multiple XPUs
    3.
    发明授权
    Memory hub providing cache coherency protocol system method for multiple processor sockets comprising multiple XPUs 有权

    公开(公告)号：US12111775B2

    公开(公告)日：2024-10-08

    申请号：US17212722

    申请日：2021-03-25

    申请人： Intel Corporation

    发明人： Duane E. Galbi ,  Matthew J. Adiletta ,  Hugh Wilkinson ,  Patrick Connor

    IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F13/42

    CPC分类号： G06F13/1621 ,  G06F13/1668 ,  G06F13/409 ,  G06F13/4221

    摘要： Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub. In some examples, based on provision of the at least some but not all home agent operations to be performed by the second home agent, the second home agent is to perform the at least some but not all home agent operations.

    Compression engine with configurable search depths and window sizes
    6.
    发明授权
    Compression engine with configurable search depths and window sizes 有权

    公开(公告)号：US12021550B2

    公开(公告)日：2024-06-25

    申请号：US17119892

    申请日：2020-12-11

    申请人： Intel Corporation

    发明人： Smita Kumar ,  Sailesh Bissessur ,  David K. Cassetti ,  Stephen T. Palermo

    IPC分类号： G06F16/00 ,  G06F16/22 ,  H03M7/30 ,  H03M7/40

    CPC分类号： H03M7/3086 ,  G06F16/2255 ,  H03M7/40

    摘要： Examples described herein relate to an encoder circuitry to apply one of multiple lossless data compression schemes on input data. In some examples, to compress input data, the encoder circuitry is to utilize a search window size and number of searches based on an applied compression scheme. In some examples, content of a memory is reconfigured to store data corresponding to a search window size of the applied compression scheme. In some examples, an applicable hash function is configured based on the applied compression scheme. In some examples, a number of searches are made for a byte position. In some examples, the encoder circuitry includes a hash table look-up and a bank decoder. In some examples, the hash table look-up is to generate a hash index to identify an address of an entry in the search window. In some examples, the bank decoder is to select a bank based on the hash index.

    Compartment isolation for load store forwarding
    7.
    发明授权
    Compartment isolation for load store forwarding 有权

    公开(公告)号：US12019733B2

    公开(公告)日：2024-06-25

    申请号：US17692464

    申请日：2022-03-11

    申请人： Intel Corporation

    发明人： Michael LeMay

    IPC分类号： G06F21/52

    CPC分类号： G06F21/52 ,  G06F2221/034

    摘要： A method comprises receiving, in a store buffer, at least a portion of a store instruction, the at least a portion of the store instruction comprising a data operand, receiving, a load instruction for execution; and determining whether the store instruction and the load instruction are in different compartments.

    Refresh command control for host assist of row hammer mitigation
    9.
    发明授权
    Refresh command control for host assist of row hammer mitigation 有权

    公开(公告)号：US11990172B2

    公开(公告)日：2024-05-21

    申请号：US18213231

    申请日：2023-06-22

    申请人： Intel Corporation

    发明人： Bill Nale ,  Christopher E. Cox

    IPC分类号： G11C11/406 ,  G06F3/06 ,  G11C11/4096

    CPC分类号： G11C11/40611 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/4096 ,  G11C11/40618

    摘要： A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

    Technologies for fast booting with error-correcting code memory
    10.
    发明授权
    Technologies for fast booting with error-correcting code memory 有权

    公开(公告)号：US11960900B2

    公开(公告)日：2024-04-16

    申请号：US16729321

    申请日：2019-12-28

    申请人： Intel Corporation

    发明人： Murugasamy K. Nachimuthu ,  Rajat Agarwal ,  Mohan J. Kumar

    IPC分类号： G06F9/44 ,  G06F9/4401 ,  G06F9/445

    CPC分类号： G06F9/4403 ,  G06F9/445

    摘要： Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.