公开(公告)号：US20190258414A1

公开(公告)日：2019-08-22

申请号：US16405296

申请日：2019-05-07

申请人： Intel Corporation

发明人： Kunal A. Khochare ,  Camille C. Raad ,  Richard P. Mangold ,  Shachi K. Thakkar

IPC分类号： G06F3/06 ,  G06F12/02

摘要： Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.

公开(公告)号：US20170168747A1

公开(公告)日：2017-06-15

申请号：US14966933

申请日：2015-12-11

申请人： Intel Corporation

发明人： Woojong Han ,  John V. Lovelace ,  Priscilla Y. Lam ,  Richard P. Mangold ,  Asher M. Altman ,  Shachi K. Thakkar

IPC分类号： G06F3/06 ,  G06F1/32

CPC分类号： G06F9/4405 ,  G06F1/24

摘要： Embodiments are generally directed to intelligent memory support for platform reset operation. An embodiment of a memory module includes a memory module controller and one or more memory banks. The memory module controller is to perform one or more internal reset processes as required for the memory module, and is to support a plurality of host platform reset processes to synchronize with the host platform.

公开(公告)号：US10915254B2

公开(公告)日：2021-02-09

申请号：US16405296

申请日：2019-05-07

申请人： Intel Corporation

发明人： Kunal A. Khochare ,  Camille C. Raad ,  Richard P. Mangold ,  Shachi K. Thakkar

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0866 ,  G06F11/16 ,  G06F11/00 ,  G06F12/0888

摘要： Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.

公开(公告)号：US10296238B2

公开(公告)日：2019-05-21

申请号：US14975160

申请日：2015-12-18

申请人： Intel Corporation

发明人： Kunal A. Khochare ,  Camille C. Raad ,  Richard P. Mangold ,  Shachi K. Thakkar

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/02

摘要： Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.