公开(公告)号：US20230090863A1

公开(公告)日：2023-03-23

申请号：US17482384

申请日：2021-09-22

申请人： Intel Corporation

发明人： Dilan SENEVIRATNE ,  Whitney BRYKS ,  Ala OMER ,  Jieying KONG ,  Sarah BLYTHE ,  Bainye Francoise ANGOUA

IPC分类号： G02B6/42 ,  G02B6/12

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques directed to dense integration of PICs in a substrate using an optical fanout structure that includes waveguides formed within a substrate to optically couple with the PICs at an edge of the substrate. One or more PICs may then be electrically with dies such as processor dies or memory dies. The one or more PICs may be located within a cavity in the substrate. The substrate may be made of glass or silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20240203664A1

公开(公告)日：2024-06-20

申请号：US18081362

申请日：2022-12-14

申请人： Intel Corporation

发明人： Yosef KORNBLUTH ,  Bainye Francoise ANGOUA ,  Whitney BRYKS ,  Daniel ROSALES-YEOMANS ,  Aaditya Anand CANDADAI ,  Holly CLINGAN ,  Jade Sharee LEWIS ,  Patrick QUACH ,  Srinivas V. PIETAMBARAM

IPC分类号： H01G4/33 ,  H01G4/10

CPC分类号： H01G4/33 ,  H01G4/105

摘要： Embodiments disclosed herein include a core for a package substrate. In an embodiment, the core comprises a first substrate with a first surface and a second surface, a first recess into the first surface of the first substrate, a first layer in the first recess, where the first layer is electrically conductive, a second layer over the first layer, where the second layer is a dielectric layer, and a third layer over the second layer, where the third layer is electrically conductive. In an embodiment, the core further comprises a second substrate with a third surface and a fourth surface, where the third surface of the second substrate faces the first surface of the first substrate, a second recess in the third surface of the second substrate, and a fourth layer in the second recess, where the fourth layer is electrically conductive, and the fourth layer contacts the third layer.

公开(公告)号：US20230086881A1

公开(公告)日：2023-03-23

申请号：US17481247

申请日：2021-09-21

申请人： Intel Corporation

发明人： Whitney BRYKS ,  Jieying KONG ,  Bainye Francoise ANGOUA ,  Junxin WANG ,  Sarah BLYTHE ,  Ala OMER ,  Dilan SENEVIRATNE

IPC分类号： G02B6/43 ,  G02B6/42

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques directed to a double-sided glass substrate, to which a PIC is hybrid bonded to a first side of the glass substrate. A die is coupled with the second side of the glass substrate opposite the first side, the PIC and the die are electrically coupled with electrically conductive through glass vias that extend from the first side of the glass substrate to the second side of the glass substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20230207503A1

公开(公告)日：2023-06-29

申请号：US17561824

申请日：2021-12-24

申请人： Intel Corporation

发明人： Jieying KONG ,  Bainye Francoise ANGOUA ,  Dilan SENEVIRATNE ,  Whitney M. BRYKS ,  Jeremy D. ECTON

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/34 ,  H01L2224/73265 ,  H01L2924/186 ,  H01L2924/01029

摘要： A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate. The metallic contact has a contact surface to make electrical contact with a trace through a dielectric layer over the semiconductor circuit substrate and the metallic contact. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The metallic contact includes a vertical lip extending vertically into the dielectric layer above the contact surface.

公开(公告)号：US20230187331A1

公开(公告)日：2023-06-15

申请号：US17549497

申请日：2021-12-13

申请人： Intel Corporation

发明人： Bainye Francoise ANGOUA ,  Chelsea GROVES ,  Frank TRUONG ,  Praneeth AKKINEPALLY ,  Whitney BRYKS

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49838 ,  H01L23/49866

摘要： Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a glass core with one or more openings with one or more dies placed in the opening such that the glass core surrounds the one or more dies. One or one or more through glass via filled with conductive material such as copper electrically couple a first side of the glass core with a second side of the glass core opposite the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US20240153857A1

公开(公告)日：2024-05-09

申请号：US17983230

申请日：2022-11-08

申请人： Intel Corporation

发明人： Bainye Francoise ANGOUA ,  Whitney BRYKS ,  Yosef KORNBLUTH ,  Daniel ROSALES-YEOMANS ,  Holly CLINGAN ,  Patrick QUACH ,  Jade Sharee LEWIS ,  Aaditya Anand CANDADAI

IPC分类号： H01L23/498 ,  H01L23/15 ,  H01L23/544

CPC分类号： H01L23/49827 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/544 ,  H01L24/16 ,  H01L2223/54426 ,  H01L2224/16225

摘要： Embodiments disclose a package substrate. In an embodiment, the package substrate comprises a core, where the core comprises: a first sub-core, where the first sub-core comprises a glass and a first through glass via (TGV), and a second sub-core, where the second sub-core comprises the glass and a second TGV. In an embodiment, the first TGV directly contacts the second TGV.

公开(公告)号：US20230091834A1

公开(公告)日：2023-03-23

申请号：US17482380

申请日：2021-09-22

申请人： Intel Corporation

发明人： Bainye Francoise ANGOUA ,  Ala OMER ,  Sarah BLYTHE ,  Junxin WANG ,  Whitney BRYKS ,  Dilan SENEVIRATNE ,  Jieying KONG

IPC分类号： G02B6/125 ,  G02B6/13

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques directed an optical waveguide formed in a glass layer. The optical waveguide may be formed by creating a first trench extending from a surface of the glass layer, and then creating a second trench extending from the bottom of the first trench, then subsequently filling the trenches with a core material which may then be topped with a cladding material. Other embodiments may be described and/or claimed.