公开(公告)号：US20230207503A1

公开(公告)日：2023-06-29

申请号：US17561824

申请日：2021-12-24

申请人： Intel Corporation

发明人： Jieying KONG ,  Bainye Francoise ANGOUA ,  Dilan SENEVIRATNE ,  Whitney M. BRYKS ,  Jeremy D. ECTON

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/34 ,  H01L2224/73265 ,  H01L2924/186 ,  H01L2924/01029

摘要： A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate. The metallic contact has a contact surface to make electrical contact with a trace through a dielectric layer over the semiconductor circuit substrate and the metallic contact. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The metallic contact includes a vertical lip extending vertically into the dielectric layer above the contact surface.

公开(公告)号：US20240217216A1

公开(公告)日：2024-07-04

申请号：US18091028

申请日：2022-12-29

申请人： INTEL CORPORATION

发明人： Kristof DARMAWIKARTA ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Dilan SENEVIRATNE ,  Jieying KONG ,  Thomas HEATON ,  Whitney BRYKS ,  Vinith BEJUGAM ,  Junxin WANG ,  Gang DUAN

IPC分类号： B32B17/10 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48

CPC分类号： B32B17/10642 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48 ,  B32B2260/04 ,  B32B2307/202 ,  B32B2457/00

摘要： Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.

公开(公告)号：US20200343175A1

公开(公告)日：2020-10-29

申请号：US16392171

申请日：2019-04-23

申请人： Intel Corporation

发明人： Zhiguo QIAN ,  Gang DUAN ,  Kemal AYGÜN ,  Jieying KONG

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/66

摘要： Embodiments include package substrates and methods of forming the package substrates. A package substrate includes a first conductive layer in a first dielectric, a second dielectric over the first dielectric, and a second conductive layer in the second dielectric, where the second conductive layer includes first and second traces. The package substrate also includes a third conductive layer over the second dielectric, and a high dielectric constant (Dk) and low DK regions in the first and second dielectrics, where the high Dk region surrounds the first traces, and where the low Dk region surrounds the second traces. The high Dk region may be between the first and third conductive layers. The low Dk region may be between the first and third conductive layers. The package substrate may include a dielectric region in the first and second dielectrics, where the dielectric region separates the high Dk and low Dk regions.

公开(公告)号：US20230090863A1

公开(公告)日：2023-03-23

申请号：US17482384

申请日：2021-09-22

申请人： Intel Corporation

发明人： Dilan SENEVIRATNE ,  Whitney BRYKS ,  Ala OMER ,  Jieying KONG ,  Sarah BLYTHE ,  Bainye Francoise ANGOUA

IPC分类号： G02B6/42 ,  G02B6/12

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques directed to dense integration of PICs in a substrate using an optical fanout structure that includes waveguides formed within a substrate to optically couple with the PICs at an edge of the substrate. One or more PICs may then be electrically with dies such as processor dies or memory dies. The one or more PICs may be located within a cavity in the substrate. The substrate may be made of glass or silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20210078296A1

公开(公告)日：2021-03-18

申请号：US16574252

申请日：2019-09-18

申请人： Intel Corporation

发明人： Jieying KONG ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Patrick QUACH ,  Dilan SENEVIRATNE

IPC分类号： B32B17/10 ,  B32B15/20 ,  H01L23/48 ,  H01L23/00

摘要： Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.

公开(公告)号：US20230420348A1

公开(公告)日：2023-12-28

申请号：US17852039

申请日：2022-06-28

申请人： Intel Corporation

发明人： Jieying KONG ,  Whitney BRYKS ,  Dilan SENEVIRATNE ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49822 ,  H01L23/49894 ,  H01L21/4857 ,  H01L2224/16225 ,  H01L24/16

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer is a dielectric material, and a trace on the first layer. In an embodiment, a pad is on the first layer, and a liner is over the first layer, the trace, and the pad, where a hole is provided through the liner. In an embodiment, the electronic package further comprises a second layer over the first layer, the trace, the pad, and the liner.

公开(公告)号：US20230098501A1

公开(公告)日：2023-03-30

申请号：US17485375

申请日：2021-09-25

申请人： Intel Corporation

发明人： Sarah BLYTHE ,  Jieying KONG ,  Peumie ABEYRATNE KURAGAMA ,  Hongxia FENG

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/532

摘要： A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate with a stress buffer dielectric between the contact and the bulk dielectric. The bulk dielectric typically covers an integrated circuit metal layer to provide electrical isolation of the circuitry. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The stress buffer dielectric has higher elongation and lower filler loading relative to the bulk dielectric, which makes the stress buffer more pliable. The stress buffer is disposed between the contact and the bulk dielectric to improve stress response, reducing the possibility of delamination of the contact from the bulk dielectric.

公开(公告)号：US20230090188A1

公开(公告)日：2023-03-23

申请号：US17481001

申请日：2021-09-21

申请人： Intel Corporation

发明人： Junxin WANG ,  Kemal AYGUN ,  Jieying KONG ,  Ala OMER ,  Whitney M. BRYKS

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/538

摘要： An apparatus is described. The apparatus includes a semiconductor chip package substrate having alternating metal and dielectric layers. First and second ones of the dielectric layers that are directly above and directly below a first of the metal layers that is patterned to have supply and/or reference voltage structures have respectively higher dielectric constant (Dk) and higher dissipation factor (Df) than third and fourth ones of the dielectric layers that are directly above and directly below a second of the metal layers that is patterned to have signal wires that are to transport signals having a pulse width of 1 ns or less.

公开(公告)号：US20230086881A1

公开(公告)日：2023-03-23

申请号：US17481247

申请日：2021-09-21

申请人： Intel Corporation

发明人： Whitney BRYKS ,  Jieying KONG ,  Bainye Francoise ANGOUA ,  Junxin WANG ,  Sarah BLYTHE ,  Ala OMER ,  Dilan SENEVIRATNE

IPC分类号： G02B6/43 ,  G02B6/42

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques directed to a double-sided glass substrate, to which a PIC is hybrid bonded to a first side of the glass substrate. A die is coupled with the second side of the glass substrate opposite the first side, the PIC and the die are electrically coupled with electrically conductive through glass vias that extend from the first side of the glass substrate to the second side of the glass substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222089A1

公开(公告)日：2024-07-04

申请号：US18090400

申请日：2022-12-28

申请人： Intel Corporation

发明人： Ala OMER ,  Peumie ABEYRATNE KURAGAMA ,  Jieying KONG ,  Wendy LIN ,  Ao WANG

IPC分类号： H01J37/32 ,  H01L21/3105

CPC分类号： H01J37/32715 ,  H01L21/31058 ,  H01J2237/2007 ,  H01J2237/20235 ,  H01J2237/334 ,  H01J2237/3355 ,  H01J2237/336 ,  H01L21/02063

摘要： This disclosure describes designs and methods for via cleaning, peeling protective film, and providing mild surface roughening and cleaning of a computer chip. A system may include a first electrode configured to generate plasma associated with cleaning vias by etching a residual material associated with smearing; an electrostatic stage configured to generate an electrostatic force associated with peeling the dielectric protective film from the semiconductor; and a stage on which the semiconductor is positioned while the electrostatic stage peels the dielectric protective film from the semiconductor, wherein the plasma is further associated with roughening a surface of the semiconductor after peeling the dielectric protective film from the semiconductor.