公开(公告)号：US20160314000A1

公开(公告)日：2016-10-27

申请号：US15103765

申请日：2013-12-23

申请人： Intel Corporation

发明人： Nikolay Kosarev ,  Sergey Y. Shishlov ,  Jayesh Iyer ,  Alexander V. Butuzov ,  Boris A. Babayan ,  Andrey Kluchnikov

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3855 ,  G06F9/3005 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3869

摘要： A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.

摘要翻译： 处理器包括执行无序指令流的第一逻辑，划分成多个线的指令流，指令流以及按程序顺序（PO）排序的每个线。 处理器还包括第二逻辑，用于确定指令流中最旧的未分配指令，并将最旧未分配指令的关联PO值存储为执行指令指针。 指令流包括调度和未分配的指令。 处理器还包括第三逻辑，用于确定指令流中最近退休的指令，并将最近退休的指令的相关联的PO值存储为退休指针;第四逻辑，用于选择退休指针和退出指令之间的指令范围; 执行指令指针，以及第五个逻辑，以标识符合退休条件的指令范围。

公开(公告)号：US10133582B2

公开(公告)日：2018-11-20

申请号：US15103765

申请日：2013-12-23

申请人： Intel Corporation

发明人： Nikolay Kosarev ,  Sergey Y. Shishlov ,  Jayesh Iyer ,  Alexander V. Butuzov ,  Boris A. Babayan ,  Andrey Kluchnikov

IPC分类号： G06F9/38 ,  G06F9/30

摘要： A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.

公开(公告)号：US20170235578A1

公开(公告)日：2017-08-17

申请号：US15391709

申请日：2016-12-27

申请人： Intel Corporation

发明人： Boris A. Babayan ,  Vladimir M. Pentkovski ,  Alexander V. Butuzov ,  Sergey Y. Shishlov ,  Alexey Y. Sivtsov ,  Nikolay Kosarev

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/34

CPC分类号： G06F9/3855 ,  G06F9/30087 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3891

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel.

公开(公告)号：US20160364237A1

公开(公告)日：2016-12-15

申请号：US15121636

申请日：2014-03-27

申请人： INTEL CORPORATION

发明人： Nikolay Kosarev ,  Sergey Y. Shishlov ,  Alexey Sivtsov ,  Boris A. Babayan ,  Alexander V. Butuzov

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3855

摘要： A processor includes logic to fetch an instruction stream divided into a plurality of strands for loading on one or more execution ports, identify a plurality of pending instructions, determine which of the strands are active, determine a program order of each of the pending instructions, and match the pending instructions to the execution ports based upon the program order of each pending instruction and whether each strand is active. Each pending instruction is at a respective head of one of the strands.

摘要翻译： 一种处理器包括用于获取被划分成多个线以用于在一个或多个执行端口上加载的指令流的逻辑，识别多个未决指令，确定所述线中的哪一个是活动的，确定每个未决指令的程序顺序， 并且基于每个挂起指令的程序顺序以及每个线是否是活动的，将待决指令与执行端口相匹配。 每个待处理的指令位于其中一条线的相应头部。