公开(公告)号：US10346170B2

公开(公告)日：2019-07-09

申请号：US14704108

申请日：2015-05-05

申请人： Intel Corporation

发明人： Jayesh Iyer ,  Jamison D. Collins ,  Sebastian Winkel

IPC分类号： G06F11/10 ,  G06F9/30 ,  G06F9/38

摘要： In one embodiment, a processor includes logic, responsive to a first instruction, to perform an operation on a first source operand and a second source operand associated with the first instruction and write a result of the operation to a destination location comprising a third source operand. The write may be a partial write of the destination location to maintain an unmodified portion of the third source operand. Other embodiments are described and claimed.

公开(公告)号：US20160314000A1

公开(公告)日：2016-10-27

申请号：US15103765

申请日：2013-12-23

申请人： Intel Corporation

发明人： Nikolay Kosarev ,  Sergey Y. Shishlov ,  Jayesh Iyer ,  Alexander V. Butuzov ,  Boris A. Babayan ,  Andrey Kluchnikov

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3855 ,  G06F9/3005 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3869

摘要： A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.

摘要翻译： 处理器包括执行无序指令流的第一逻辑，划分成多个线的指令流，指令流以及按程序顺序（PO）排序的每个线。 处理器还包括第二逻辑，用于确定指令流中最旧的未分配指令，并将最旧未分配指令的关联PO值存储为执行指令指针。 指令流包括调度和未分配的指令。 处理器还包括第三逻辑，用于确定指令流中最近退休的指令，并将最近退休的指令的相关联的PO值存储为退休指针;第四逻辑，用于选择退休指针和退出指令之间的指令范围; 执行指令指针，以及第五个逻辑，以标识符合退休条件的指令范围。

公开(公告)号：US10241794B2

公开(公告)日：2019-03-26

申请号：US15391703

申请日：2016-12-27

申请人： Intel Corporation

发明人： Sergey P. Scherbinin ,  Jayesh Iyer ,  Alexander Y. Ostanevich ,  Dmitry Maslennikov ,  Denis G. Motin ,  Alexander V. Ermolovich ,  Andrey Chudnovets ,  Sergey A. Rozhkov ,  Boris A. Babayan

IPC分类号： G06F9/44 ,  G06F9/54 ,  G06F9/32 ,  G06F8/41 ,  G06F9/38 ,  G06F9/30 ,  G06F9/455

摘要： Embodiments described herein generally relate to the field of multi-strand out-of-order loop processing, and, more specifically, to apparatus and methods to support counted loop exits in a multi-strand loop processor. In one embodiment, a processor includes a loop accelerator comprising a strand documentation buffer and a plurality of strand execution circuits; and a binary translator to receive a plurality of loop instructions, divide the plurality of loop instructions into a plurality of strands, and store a strand documentation for each of the plurality of strands into the strand documentation buffer, each strand documentation indicating at least a number of iterations; wherein the binary translator further causes the loop accelerator to execute the plurality of strands asynchronously and in parallel using the plurality of strand execution circuits, wherein each of the strand execution circuits repeats the strand for the number of iterations indicated in the strand documentation associated with the strand.

公开(公告)号：US20160179538A1

公开(公告)日：2016-06-23

申请号：US14576915

申请日：2014-12-19

申请人： Intel Corporation

发明人： JAMISON D. COLLINS ,  Jayesh Iyer ,  Sebastian Winkel ,  Polychronis Xekalakis ,  Howard H. Chen ,  Rupert Brauch

IPC分类号： G06F9/30

CPC分类号： G06F9/30134 ,  G06F8/41 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3859 ,  G06F9/3863

摘要： Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.

摘要翻译： 用于使用堆栈同步指令来实现和维护谓词值堆栈的方法和装置的实施例。 在一个实施例中，该装置是一种无序的硬件/软件协同设计的处理器，其包括明确地管理谓词寄存器堆栈以便在执行的分支之间保持堆栈一致性的指令，其将可变数量的谓词值推送到谓词堆栈。 在一个实施例中，基于栈的谓词寄存器实现能够通过早期重命名谓词寄存器来实现早期分支计算和早期分支错误预测恢复。

公开(公告)号：US10133582B2

公开(公告)日：2018-11-20

申请号：US15103765

申请日：2013-12-23

申请人： Intel Corporation

发明人： Nikolay Kosarev ,  Sergey Y. Shishlov ,  Jayesh Iyer ,  Alexander V. Butuzov ,  Boris A. Babayan ,  Andrey Kluchnikov

IPC分类号： G06F9/38 ,  G06F9/30

摘要： A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.

公开(公告)号：US20180181400A1

公开(公告)日：2018-06-28

申请号：US15391703

申请日：2016-12-27

申请人： Intel Corporation

发明人： Sergey P. Scherbinin ,  Jayesh Iyer ,  Alexander Y. Ostanevich ,  Dmitry Maslennikov ,  Denis G. Motin ,  Alexander V. Ermolovich ,  Andrey Chudnovets ,  Sergey A. Rozhkov ,  Boris A. Babayan

IPC分类号： G06F9/32

CPC分类号： G06F9/325 ,  G06F8/443 ,  G06F8/4452 ,  G06F8/452 ,  G06F9/30065 ,  G06F9/381 ,  G06F9/3851 ,  G06F9/45516

摘要： Embodiments described herein generally relate to the field of multi-strand out-of-order loop processing, and, more specifically, to apparatus and methods to support counted loop exits in a multi-strand loop processor. In one embodiment, a processor includes a loop accelerator comprising a strand documentation buffer and a plurality of strand execution circuits; and a binary translator to receive a plurality of loop instructions, divide the plurality of loop instructions into a plurality of strands, and store a strand documentation for each of the plurality of strands into the strand documentation buffer, each strand documentation indicating at least a number of iterations; wherein the binary translator further causes the loop accelerator to execute the plurality of strands asynchronously and in parallel using the plurality of strand execution circuits, wherein each of the strand execution circuits repeats the strand for the number of iterations indicated in the strand documentation associated with the strand.

公开(公告)号：US09904546B2

公开(公告)日：2018-02-27

申请号：US14750940

申请日：2015-06-25

申请人： Intel Corporation

发明人： Jayesh Iyer ,  Jamison D. Collins ,  Sebastian Winkel ,  Howard H. Chen

IPC分类号： G06F9/30

CPC分类号： G06F9/30029 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3013

摘要： A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

公开(公告)号：US10241801B2

公开(公告)日：2019-03-26

申请号：US15390194

申请日：2016-12-23

申请人： Intel Corporation

发明人： Jayesh Iyer ,  Sergey P. Scherbinin ,  Alexander Y. Ostanevich ,  Dmitry M. Maslennikov ,  Denis G. Motin ,  Alexander V. Ermolovich ,  Andrey Chudnovets ,  Sergey A. Rozhkov ,  Boris A. Babayan

IPC分类号： G06F9/302 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F8/41

摘要： An apparatus includes a register file and a binary translator to create a plurality of strands and a plurality of iteration windows, where each iteration window of the plurality of iteration windows is allocated a set of continuous registers of the register file. The apparatus further includes a buffer to store strand documentation for a strand from the plurality of strands, where the strand documentation for the strand is to include an indication of a current register base for the strand. The apparatus further includes an execution circuit to execute an instruction to update the current register base for the strand in the strand documentation for the strand based on a fixed step value and an iteration window size.

公开(公告)号：US20160378472A1

公开(公告)日：2016-12-29

申请号：US14750940

申请日：2015-06-25

申请人： Intel Corporation

发明人： Jayesh Iyer ,  Jamison D. Collins ,  Sebastian Winkel ,  Howard H. Chen

IPC分类号： G06F9/30

CPC分类号： G06F9/30029 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3013

摘要： A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

摘要翻译： 处理器包括用于接收指令的前端。 处理器还包括执行指令的核心。 核心包括执行指令的基本功能以产生结果的逻辑，基于指令中的预测设置产生结果的比较的谓词值，并将谓词值设置在寄存器中。 该处理器还包括一个退休单位退休指导。

公开(公告)号：US09471501B2

公开(公告)日：2016-10-18

申请号：US14498902

申请日：2014-09-26

申请人： INTEL CORPORATION

发明人： Andrey Kluchnikov ,  Jayesh Iyer ,  Sergey Y. Shishlov ,  Boris A. Babayan

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F13/18

CPC分类号： G06F12/0844 ,  G06F3/0613 ,  G06F3/0637 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F13/18 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/251 ,  G06F2212/452

摘要： Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

摘要翻译： 描述了控制对多存储体数据缓存的访问的方法和装置。 在一个实施例中，处理器包括冲突解决逻辑，以检测被调度以在相同时钟周期内访问多存储体数据高速缓存的相同存储体的多个指令，并且为预定访问最高总数的多个指令的指令授予访问优先级 银行多银行数据缓存。 在另一个实施例中，一种方法包括检测被调度以在相同时钟周期内访问多存储体数据高速缓存的同一个存储体的多个指令，以及授予被调度以访问该多个存储体中多个存储体的最高总数组的多个指令的指令的访问优先级 银行数据缓存。