专利检索 ap:("Intel Corporation") AND inv:"Alexey Y. Sivtsov" 第 1 页

1.

发明申请
Method and Apparatus for Scheduling of Instructions in a Multi-Strand Out-Of-Order Processor 审中-公开

公开(公告)号：US20170235578A1

公开(公告)日：2017-08-17

申请号：US15391709

申请日：2016-12-27

申请人： Intel Corporation

发明人： Boris A. Babayan , Vladimir M. Pentkovski , Alexander V. Butuzov , Sergey Y. Shishlov , Alexey Y. Sivtsov , Nikolay Kosarev

IPC分类号： G06F9/38 , G06F9/30 , G06F9/34

CPC分类号： G06F9/3855 , G06F9/30087 , G06F9/3016 , G06F9/3017 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3838 , G06F9/3851 , G06F9/3891

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel.

2.

发明授权
Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order 有权

公开(公告)号：US09632790B2

公开(公告)日：2017-04-25

申请号：US13993794

申请日：2012-12-26

申请人： Intel Corporation

发明人： Jayesh Iyer , Nikolay Kosarev , Sergey Y. Shishlov , Alexey Y. Sivtsov , Yuriy V Baida , Alexander V Butuzov , Bob Babayan , Vladimir Pentkovski

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 , G06F9/3851 , G06F9/3855

摘要： A processing device comprises select logic to schedule a plurality of instructions for execution. The select logic calculates a reconstructed program order (RPO) value for each of a plurality of instructions that are ready to be scheduled for execution. The select logic creates an ordered list of instructions based on the delayed RPO values, the delayed RPO values comprising the calculated RPO values from a previous execution cycle, and dispatches instructions for scheduling based on the ordered list.