公开(公告)号：US09196577B2

公开(公告)日：2015-11-24

申请号：US14151110

申请日：2014-01-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer ,  Jürgen Schredl ,  Xaver Schlögel ,  Klaus Schiess

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.

Abstract translation: 半导体封装装置包括晶体管器件，其包括包括源电极和栅电极的第一侧，具有第一表面的管芯焊盘和具有第一表面的引线。 第一导电构件设置在源电极和管芯焊盘的第一表面之间，并将源极与管芯焊盘的第一表面隔开一定距离，该距离大于栅电极与第一表面之间的距离 铅。

公开(公告)号：US20150041859A1

公开(公告)日：2015-02-12

申请号：US13962622

申请日：2013-08-08

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer

IPC: H01L23/522 ,  H01L29/778

CPC classification number: H01L23/5226 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/48091 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/0761 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09972 ,  H01L2924/00014

Abstract: A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.

Abstract translation: 再分配板包括：第一导电层，包括用于低电压信号的再分配结构;第二导电层，包括用于高电压信号的再分配结构;以及非导电层。 第二导电层通过非导电层与第一导电层间隔开。 再分配板还包括从再分布板的安装表面延伸到第二导电层的导电连接器。 导电连接器被第一导电层的低电压迹线围绕。

公开(公告)号：US20230230903A1

公开(公告)日：2023-07-20

申请号：US18085746

申请日：2022-12-21

Applicant: Infineon Technologies AG

Inventor： Hooi Boon TEOH ,  Hao ZHUANG ,  Oliver BLANK ,  Paul Armand CALO ,  Markus DINKEL ,  Josef Höglauer ,  Daniel Hölzl ,  Wee Aun JASON LIM ,  Gerhard Thomas Nöbauer ,  Ralf OTREMBA ,  Martin Pölzl ,  Ying Pok SAM ,  Xaver Schlögel ,  Chee Voon TAN

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L24/32 ,  H01L24/05 ,  H01L24/03 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/291 ,  H01L24/29 ,  H01L2224/26145 ,  H01L2224/04026 ,  H01L2224/0361 ,  H01L2224/83801

Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.

公开(公告)号：US20150194373A1

公开(公告)日：2015-07-09

申请号：US14151110

申请日：2014-01-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer ,  Jürgen Schredl ,  Xaver Schlögel ,  Klaus Schiess

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.

Abstract translation: 半导体封装装置包括晶体管器件，其包括包括源电极和栅电极的第一侧，具有第一表面的管芯焊盘和具有第一表面的引线。 第一导电构件设置在源电极和管芯焊盘的第一表面之间，并将源极与管芯焊盘的第一表面隔开一定距离，该距离大于栅电极与第一表面之间的距离 铅。

公开(公告)号：US20230197577A1

公开(公告)日：2023-06-22

申请号：US18082238

申请日：2022-12-15

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Josef Höglauer ,  Angela Kessler ,  Claus Waechter

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/16 ,  H01L25/00

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/49534 ,  H01L25/16 ,  H01L25/50

Abstract: A semiconductor device includes a premolded leadframe, including a main surface, at least one electrical contact extending out of the main surface, and an opposite main surface arranged opposite to the main surface. The semiconductor device further includes a semiconductor package arranged on the main surface and laterally displaced to the at least one electrical contact of the premolded leadframe. The semiconductor package includes a semiconductor chip and at least one electrical contact. Surfaces of the at least one electrical contact of the premolded leadframe and the at least one electrical contact of the semiconductor package facing away from the main surface are flush.

公开(公告)号：US08975735B2

公开(公告)日：2015-03-10

申请号：US13962622

申请日：2013-08-08

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/06 ,  H01L21/00 ,  H05K7/00 ,  H01L23/522 ,  H01L29/778

CPC classification number: H01L23/5226 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/48091 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/0761 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09972 ,  H01L2924/00014

Abstract: A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.

Abstract translation: 再分配板包括：第一导电层，包括用于低电压信号的再分配结构;第二导电层，包括用于高电压信号的再分配结构;以及非导电层。 第二导电层通过非导电层与第一导电层间隔开。 再分配板还包括从再分布板的安装表面延伸到第二导电层的导电连接器。 导电连接器被第一导电层的低电压迹线围绕。