-
公开(公告)号：US20220102263A1
公开(公告)日：2022-03-31
申请号：US17459296
申请日：2021-08-27
发明人： Chee Yang Ng , Stefan Woetzel , Edward Fuergut , Thai Kee Gan , Chee Hong Lee , Jayaganasan Narayanasamy , Ralf Otremba
IPC分类号： H01L23/498 , H01L23/00
摘要： A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.
-
公开(公告)号：US10777536B2
公开(公告)日：2020-09-15
申请号：US16213478
申请日：2018-12-07
发明人： Chau Fatt Chiang , April Coleen Tuazon Bernardez , Junny Abdul Wahid , Roslie Saini bin Bakar , Kon Hoe Chin , Hock Heng Chong , Kok Yau Chua , Hsieh Ting Kuek , Chee Hong Lee , Soon Lee Liew , Nurfarena Othman , Pei Luan Pok , Werner Reiss , Stefan Schmalzl
IPC分类号： H01L25/075 , H01L25/065 , H01L23/498 , B81B7/00 , H01L23/31 , B81C1/00 , H01L23/10
摘要： Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.
-
公开(公告)号：US20240312956A1
公开(公告)日：2024-09-19
申请号：US18122776
申请日：2023-03-17
发明人： Pei Luan Pok , Swee Kah Lee , Soon Lock Goh , Chee Hong Lee , Samsun Paing , Chee Chiew Chong
CPC分类号： H01L24/96 , H01L21/4821 , H01L21/561 , H01L21/568 , H01L24/11 , H01L2224/11 , H01L2224/96
摘要： A method of forming a semiconductor package includes providing a baseplate, mounting a semiconductor die on the baseplate with a main surface of the semiconductor die facing away from the baseplate, forming vertical interconnect elements on the main surface of the semiconductor die, forming an encapsulant on the baseplate that encapsulates the semiconductor die, exposing the vertical interconnect elements at an upper surface of the encapsulant, forming a first level metal pad on the upper surface of the encapsulant that contacts the exposed vertical interconnect elements, and forming structured metal regions on the upper surface of the encapsulant, wherein forming the structured metal regions includes structuring the first level metal pad.
-
4.发明申请公开(公告)号：US20220375883A1
公开(公告)日：2022-11-24
申请号：US17741597
申请日：2022-05-11
IPC分类号： H01L23/64 , H01L49/02 , H01L23/498 , H01L21/56 , H01L21/48
摘要： A method for fabricating an electrical or electronic device package includes providing a first plateable encapsulation layer; activating first selective areas on a main surface of the first plateable encapsulation layer; forming a first metallization layer by electrolytic or electroless plating on the first activated areas; and fabricating a passive electrical component on the basis of the first metallization layer.
-
公开(公告)号：US20210313294A1
公开(公告)日：2021-10-07
申请号：US17210693
申请日：2021-03-24
发明人： Chau Fatt Chiang , Xavier Arokiasamy , Naveendran Chellamuthu , Chee Chiew Chong , Joo Ming Goa , Chee Hong Lee , Muhammat Sanusi Muhammad , Chee Voon Tan , Wee Boon Tay
IPC分类号： H01L23/00 , H01L21/48 , H01L23/495
摘要： A semiconductor package includes a carrier having a recess, a semiconductor die arranged on the carrier such that a first side of the semiconductor die faces the carrier, and a contact clip arranged over a second side of the semiconductor die, opposite the first side. The contact clip includes a lowered part. The lowered part is arranged in the recess.
-
公开(公告)号：US11984392B2
公开(公告)日：2024-05-14
申请号：US17459296
申请日：2021-08-27
发明人： Chee Yang Ng , Stefan Woetzel , Edward Fuergut , Thai Kee Gan , Chee Hong Lee , Jayaganasan Narayanasamy , Ralf Otremba
IPC分类号： H01L23/498 , H01L23/00 , H01L23/373 , H01L23/492 , H01L23/538 , H01L29/66 , H01L23/31
CPC分类号： H01L23/49844 , H01L23/3735 , H01L23/4924 , H01L23/5383 , H01L24/05 , H01L24/08 , H01L24/14 , H01L24/16 , H01L29/66431 , H01L23/3185 , H01L23/49827 , H01L24/06 , H01L24/32 , H01L2224/0556 , H01L2224/0603 , H01L2224/06181 , H01L2224/32227 , H01L2924/13055 , H01L2924/13064 , H01L2924/13091
摘要： A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.
-
公开(公告)号：US11791169B2
公开(公告)日：2023-10-17
申请号：US16993867
申请日：2020-08-14
发明人： Pei Luan Pok , Roslie Saini bin Bakar , Chau Fatt Chiang , Chee Hong Lee , Swee Kah Lee , Yu Shien Leong , Jan Sing Loh , Yean Seng Ng
IPC分类号： H01L21/56 , H01L23/29 , H01L23/31 , H01L23/498 , H01L23/495
CPC分类号： H01L21/56 , H01L23/295 , H01L23/3107 , H01L23/49838 , H01L23/49861 , H01L23/495 , H01L2924/181
摘要： A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.
-
公开(公告)号：US11274984B2
公开(公告)日：2022-03-15
申请号：US16890461
申请日：2020-06-02
发明人： Chau Fatt Chiang , Paul Armand Asentista Calo , Chan Lam Cha , Kok Yau Chua , Jo Ean Chye , Chee Hong Lee , Swee Kah Lee , Theng Chao Long , Jayaganasan Narayanasamy , Khay Chwan Saw
摘要： A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.
-
公开(公告)号：US20230170226A1
公开(公告)日：2023-06-01
申请号：US17536538
申请日：2021-11-29
发明人： Chau Fatt Chiang , Thorsten Meyer , Chan Lam Cha , Wern Ken Daryl Wee , Chee Hong Lee , Swee Kah Lee , Norliza Morban , Khay Chwan Andrew Saw
IPC分类号： H01L21/48 , H01L23/31 , H01L23/498 , H01L23/367 , H01L21/56 , H01L25/00 , H01L25/18
CPC分类号： H01L21/4853 , H01L23/31 , H01L23/49811 , H01L23/367 , H01L21/568 , H01L25/50 , H01L25/18
摘要： A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.
-
公开(公告)号：US20210050227A1
公开(公告)日：2021-02-18
申请号：US16993867
申请日：2020-08-14
发明人： Pei Luan Pok , Roslie Saini bin Bakar , Chau Fatt Chiang , Chee Hong Lee , Swee Kah Lee , Yu Shien Leong , Jan Sing Loh , Yean Seng Ng
摘要： A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.015 秒)
