公开(公告)号：US20220005768A1

公开(公告)日：2022-01-06

申请号：US17216686

申请日：2021-03-30

Applicant: Industrial Technology Research Institute

Inventor： Jui-Wen Yang ,  Hsin-Cheng Lai ,  Chieh-Wei Feng ,  Tai-Jui Wang ,  Yu-Hua Chung ,  Tzu-Yang Ting

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/64

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

公开(公告)号：US20190355713A1

公开(公告)日：2019-11-21

申请号：US16183735

申请日：2018-11-08

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Yu-Hua Chung

IPC: H01L27/02 ,  H02H9/04 ,  H01L23/538

Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.

公开(公告)号：US09012314B2

公开(公告)日：2015-04-21

申请号：US13710795

申请日：2012-12-11

Applicant: Industrial Technology Research Institute

Inventor： Wen-Ching Sun ,  Sheng-Min Yu ,  Tai-Jui Wang ,  Tzer-Shen Lin

IPC: H01L21/22 ,  H01L21/38 ,  H01L21/225 ,  H01L31/068 ,  H01L31/18

CPC classification number: H01L21/225 ,  H01L21/22 ,  H01L21/2255 ,  H01L31/068 ,  H01L31/18 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method for forming doping regions is disclosed, including providing a substrate, forming a first-type doping material on the substrate and forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap; forming a covering layer to cover the substrate, the first-type doping material and the second-type doping material; and performing a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate.

Abstract translation: 公开了一种用于形成掺杂区域的方法，包括提供衬底，在衬底上形成第一类掺杂材料，并在衬底上形成第二类掺杂材料，其中第一类型掺杂材料与第二类掺杂材料分离 掺杂材料缺口; 形成覆盖所述基板的覆盖层，所述第一类型掺杂材料和所述第二类型掺杂材料; 并且进行热扩散处理以将第一种掺杂材料和第二类型掺杂材料扩散到衬底中。

公开(公告)号：US11764166B2

公开(公告)日：2023-09-19

申请号：US17216686

申请日：2021-03-30

Applicant: Industrial Technology Research Institute ,  Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Wen Yang ,  Hsin-Cheng Lai ,  Chieh-Wei Feng ,  Tai-Jui Wang ,  Yu-Hua Chung ,  Tzu-Yang Ting

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/08 ,  H01L2224/08235

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

公开(公告)号：US10950588B2

公开(公告)日：2021-03-16

申请号：US16027374

申请日：2018-07-05

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Wei-Yuan Cheng

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/538 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L29/786

Abstract: A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.

公开(公告)号：US20190013378A1

公开(公告)日：2019-01-10

申请号：US15691755

申请日：2017-08-31

Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

Inventor： Tai-Jui Wang ,  Chieh-Wei Feng ,  Meng-Jung Yang ,  Wei-Han Chen ,  Shao-An Yan ,  Tsu-Chiang Chang

IPC: H01L27/32

CPC classification number: H01L27/3276 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3272 ,  H01L2227/323

Abstract: A pixel structure including a substrate, a power wire, a planarization layer, a drive circuit and a conductive structure is provided. The substrate has a layout area and a light-transmitting area located outside the layout area. The power wire is disposed on the layout area of the substrate. The power wire includes a shielding layer. The planarization layer is disposed on the substrate and covers the power wire. The drive circuit is disposed on the planarization layer and corresponds to the layout area. The drive circuit includes a first active device. The shielding layer overlaps with the first active device. The conductive structure is disposed in the planarization layer and distributed corresponding to the layout area. The power wire is electrically connected with the drive circuit through the conductive structure. A display panel is also provided.

公开(公告)号：US10083989B2

公开(公告)日：2018-09-25

申请号：US15209780

申请日：2016-07-14

Applicant: Industrial Technology Research Institute

Inventor： Tai-Jui Wang ,  Tsu-Chiang Chang ,  Yu-Hua Chung ,  Wei-Han Chen ,  Hsiao-Chiang Yao

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1218 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device is provided to include a flexible substrate, a barrier layer, a heat insulating layer, a device layer, a dielectric material later and a stress absorbing layer. The barrier layer is disposed on the flexible substrate. The heat insulating layer is disposed on the barrier layer, wherein the heat insulating layer has a thermal conductivity of less than 20 W/mK. The device layer is disposed on the heat insulating layer. The dielectric material layer is disposed on the device layer, and the dielectric material layer and the heat insulating layer include at least one trench. The stress absorbing layer is disposed on the dielectric material layer, and the stress absorbing layer fills into the at least one trench.

公开(公告)号：US20240088004A1

公开(公告)日：2024-03-14

申请号：US18452566

申请日：2023-08-21

Applicant: Industrial Technology Research Institute

Inventor： Tai-Jui Wang ,  Jui-Wen Yang ,  Chieh-Wei Feng ,  Chih Wei Lu ,  Hsien-Wei Chiu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49822 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838

Abstract: A stacked wiring structure includes a first wiring substrate and a second wiring substrate. The first wiring substrate includes a first glass substrate, multiple first conductive through vias penetrating through the first glass substrate, and a first multi-layered redistribution wiring structure disposed on the first glass substrate. The second wiring substrate includes a second glass substrate, multiple second conductive through vias penetrating through the second glass substrate, and a second multi-layered redistribution wiring structure disposed on the second glass substrate. The first conductive through vias are electrically connected to the second conductive through vias. The first glass substrate is spaced apart from the second glass substrate. The first multi-layered redistribution wiring structure is spaced apart from the second multi-layered redistribution wiring structure by the first glass substrate and the second glass substrate.

公开(公告)号：US11776920B2

公开(公告)日：2023-10-03

申请号：US17158014

申请日：2021-01-26

Applicant: Industrial Technology Research Institute

Inventor： Tzu-Yang Ting ,  Chieh-Wei Feng ,  Tai-Jui Wang

IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H03H7/01 ,  H01G4/30 ,  H01G4/012 ,  H01G4/40 ,  H01F27/40 ,  H01L23/552

CPC classification number: H01L23/642 ,  H01F27/40 ,  H01G4/012 ,  H01G4/30 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/552 ,  H01L23/645 ,  H01L28/60 ,  H03H7/0115

Abstract: Provided a filter and a redistribution layer structure including the same. The capacitor includes a first electrode, a second electrode, a third electrode, a dielectric layer, and a conductive through via. The second electrode is disposed above the first electrode. The third electrode is disposed between the first electrode and the second electrode. The dielectric layer is disposed between the first electrode and the third electrode and between the second electrode and the third electrode. The conductive through via penetrates the dielectric layer and the third electrode to be connected to the first electrode and the second electrode, and is electrically separated from the third electrode. The first electrode and the second electrode are signal electrodes, and the third electrode is a ground electrode.

公开(公告)号：US20230165529A1

公开(公告)日：2023-06-01

申请号：US17584394

申请日：2022-01-26

Applicant: Industrial Technology Research Institute

Inventor： Yu-Hua Chung ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Tzu-Yang Ting ,  Jui-Wen Yang

IPC: A61B5/00 ,  A61B5/263 ,  A61B5/277 ,  A61B5/271

CPC classification number: A61B5/683 ,  A61B5/7203 ,  A61B5/263 ,  A61B5/277 ,  A61B5/271 ,  A61B2562/046

Abstract: A physiological sensing device is provided, including an electronic component, a coupled sensing electrode, a coupling dielectric layer, and a wire layer. The coupled sensing electrode is configured to sense a physiological signal of an object, wherein there is a capacitance value between the object and the coupled sensing electrode. The coupling dielectric layer is disposed under the coupled sensing electrode, so that the capacitance value is between 1 nF and 10 nF. The wire layer is electrically connected to the electronic component and the coupled sensing electrode.