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    CONTROLLING OPERATION OF MULTIPLE COMPUTATIONAL ENGINES
    4.
    发明申请
    CONTROLLING OPERATION OF MULTIPLE COMPUTATIONAL ENGINES 审中-公开

    公开(公告)号：US20200334175A1

    公开(公告)日：2020-10-22

    申请号：US16389530

    申请日：2019-04-19

    Applicant: International Business Machines Corporation

    Inventor： William Santiago-Fernandez ,  Tamas Visegrady ,  Silvio Dragone ,  Michael Charles Osborne

    IPC: G06F13/16 ,  H04L9/08 ,  G06F21/62 ,  G06F9/30 ,  G06F9/4401

    Abstract: The present disclosure relates to a computer-implemented method for controlling operation of multiple computational engines of a physical computing device. The computer-implemented method includes providing a multiplexer module in the device, the multiplexer module including a first and second memory region. The multiplexer module may receive from a first driver at the multiplexer module a data processing request to be processed by a first set of one or more computational engines of the computational engines. Subsequent to receiving the data processing request, the multiplexer module may assign a request sub-region of the first region and a response sub-region of the second region to the first driver. Data indicative of the request sub-region and the response sub-region may be submitted to the first driver. Results of processing the request may be received at the response sub-region.

    Vented tamper-respondent assemblies
    5.
    发明授权
    Vented tamper-respondent assemblies 有权

    公开(公告)号：US10299372B2

    公开(公告)日：2019-05-21

    申请号：US15275748

    申请日：2016-09-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Silvio Dragone ,  Stefano S. Oggioni ,  William Santiago-Fernandez

    IPC: H05K1/02 ,  H05K1/18 ,  H05K3/30 ,  G06F21/87

    Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include a multilayer circuit board, a tamper-detection sensor, and a vent structure. The tamper-detection sensor is embedded within the multilayer circuit board, and defines, at least in part, a secure volume associated with the multilayer circuit board. The vent structure is incorporated into the multilayer circuit board, and includes at least one vent channel. The vent channel(s) is in fluid communication with a space within the secure volume to facilitate venting the space of the secure volume. The space within the secure volume may accommodate, for instance, one or more electronic components to be protected, and the at least one vent channel may, for instance, allow air pressure within the space of the secure volume to equalize with air pressure external to the tamper-respondent assembly.

    Multi-layer stack with embedded tamper-detect protection
    7.
    发明授权
    Multi-layer stack with embedded tamper-detect protection 有权

    公开(公告)号：US10169967B1

    公开(公告)日：2019-01-01

    申请号：US16048622

    申请日：2018-07-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： James A. Busby ,  Phillip Duane Isaacs ,  William Santiago-Fernandez

    IPC: G08B13/12

    Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

    Code updates in processing systems
    8.
    发明授权
    Code updates in processing systems 有权
    处理系统中的代码更新

    公开(公告)号：US09575769B2

    公开(公告)日：2017-02-21

    申请号：US14679533

    申请日：2015-04-06

    Applicant: International Business Machines Corporation

    Inventor： Vincenzo Condorelli ,  Silvio Dragone ,  William Santiago-Fernandez ,  Tamas Visegrady

    IPC: G06F9/00 ,  G06F15/177 ,  G06F9/44 ,  G06F21/57 ,  G06F12/02 ,  G06F13/40 ,  G06F9/445 ,  G05B19/05 ,  G06F11/14

    CPC classification number: G06F9/4403 ,  G05B19/056 ,  G06F8/63 ,  G06F8/65 ,  G06F8/654 ,  G06F9/4401 ,  G06F9/44505 ,  G06F11/1433 ,  G06F12/0246 ,  G06F13/4022 ,  G06F21/575

    Abstract: A method for updating code images in a system includes booting a first image of a code with a sub-system processor, receiving a second image of the code, performing a security and reliability check of the second image of the code with the sub-system processor, determining whether the security and reliability check of the second image of the code is successful, storing the second image of the code in a first memory device responsive to determining that the security and reliability check of the second image of the code is successful, designating the second image of the code as an active image, and sending the second image of the code to a second memory device, the second memory device communicatively connected with the first memory device and a main processor.

    Abstract translation: 一种用于更新系统中的代码图像的方法包括用子系统处理器引导代码的第一图像，接收代码的第二图像，使用子系统执行代码的第二图像的安全性和可靠性检查 处理器，确定代码的第二图像的安全性和可靠性检查是否成功，将代码的第二图像存储在第一存储器设备中，以响应于确定代码的第二图像的安全性和可靠性检查成功， 将代码的第二图像指定为活动图像，以及将代码的第二图像发送到第二存储器设备，与第一存储器设备和主处理器通信地连接的第二存储器设备。

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